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Hierarchical Verification Using an MDGHOL Hybrid Tool
"... We describe a hybrid formal hardware verification tool that links the HOL interactive proof system and the MDG automated hardware verification tool. It supports a hierarchical verification approach that mirrors the hierarchical structure of designs. We obtain advantages of both verification paradi ..."
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Cited by 8 (2 self)
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We describe a hybrid formal hardware verification tool that links the HOL interactive proof system and the MDG automated hardware verification tool. It supports a hierarchical verification approach that mirrors the hierarchical structure of designs. We obtain advantages of both verification paradigms. We illustrate its use by considering a component of a communications chip. Verification with the hybrid tool is significantly faster and more tractable than using either tool alone.
Proving existential theorems when importing results from MDG to HOL
 TPHOLS 2001 SUPPLEMENTAL PROCEEDINGS, INFORMATIC RESEARCH REPORT EDIINFRR0046
, 2001
"... An existential theorem, for the specification or implementation of hardware, states that for any inputs there must exist at least one output which is consistent with it. It is proved to prevent an inconsistent model being produced and it is required to formally import the verification result from on ..."
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Cited by 4 (3 self)
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An existential theorem, for the specification or implementation of hardware, states that for any inputs there must exist at least one output which is consistent with it. It is proved to prevent an inconsistent model being produced and it is required to formally import the verification result from one verification system to another system. In this paper, we investigate the verification of the existential theorems of hardware specifications and implementations. Whilst much of the approach is generally applicable, we specifically consider a hybrid system linking the MDG hardware verification system with the HOL interactive proof system. We investigate existential theorems based on the syntax and semantics of the MDG input language (MDGHDL) in HOL. We define an output representation for each component in the MDGHDL component library. We summarize a general method which is used to prove the existential theorem for any MDGHDL program. The method can also be used to solve other existentially quantified goals.
Providing a Formal Linkage between MDG and HOL
, 2002
"... We describe an approach for formally verifying the linkage between a symbolic state enumeration system and a theorem proving system. This involves the following three stages of proof. Firstly we prove theorems about the correctness of the translation part of the symbolic state system. It interface ..."
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Cited by 2 (2 self)
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We describe an approach for formally verifying the linkage between a symbolic state enumeration system and a theorem proving system. This involves the following three stages of proof. Firstly we prove theorems about the correctness of the translation part of the symbolic state system. It interfaces between low level decision diagrams and high level description languages. We ensure that the semantics of a program is preserved in those of its translated form. Secondly we prove linkage theorems: theorems that justify introducing a result from a state enumeration system into a proof system. Finally we combine the translator correctness and linkage theorems. The resulting new linkage theorems convert results to a high level language from the low level decision diagrams that the result was actually proved about in the state enumeration system.They justify importing lowlevel external verification results into a theorem prover. We use a linkage between the HOL system and a simplified version of the MDG system to illustrate the ideas and consider a small example that integrates two applications from MDG and HOL to illustrate the linkage theorems.
Embedding and Verification of an MDGHDL Translator in HOL
, 2000
"... We investigate the verification of a translation phase of the Multiway Decision Graphs (MDG) verification system using the Higher Order Logic (HOL) theorem prover. In this paper, we deeply embed the semantics of a subset of the MDGHDL language and its Table subset into HOL. We define a set of funct ..."
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Cited by 2 (1 self)
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We investigate the verification of a translation phase of the Multiway Decision Graphs (MDG) verification system using the Higher Order Logic (HOL) theorem prover. In this paper, we deeply embed the semantics of a subset of the MDGHDL language and its Table subset into HOL. We define a set of functions which translate this subset MDGHDL language to its Table subset. A correctness theorem for this translator, which quantifies over its syntactic structure, has been proved. This theorem states that the semantics of the MDGHDL program is equivalent to the semantics of its Table subset.
Formally Linking MDG and HOL Based on a Verified MDG System
"... We describe an approach for formally linking a symbolic state enumeration system and a theorem proving system based on a verified version of the former. It has been realized using a simplified version of the MDG system and the HOL system. Firstly, we have verified aspects of correctness of a simp ..."
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Cited by 1 (0 self)
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We describe an approach for formally linking a symbolic state enumeration system and a theorem proving system based on a verified version of the former. It has been realized using a simplified version of the MDG system and the HOL system. Firstly, we have verified aspects of correctness of a simplified version of the MDG system. We have made certain that the semantics of a program is preserved in those of its translated form. Secondly, we have provided a formal linkage between the MDG system and the HOL system based on importing theorems. The MDG verification results can be formally imported into HOL to form a HOL theorem. Thirdly, we have combined the translator correctness theorems and importing theorems. This allows the MDG verification results to be imported in terms of a high level language (MDGHDL) rather than a low level language. We also summarize a general method to prove existential theorems for the design. The feasibility of this approach is demonstrated in a case study that integrates two applications: hardware verification (in MDG) and usability verification (in HOL). A single HOL theorem is proved that integrates the two results.
Providing a Formal Linkage between MDG and
, 2002
"... The contribution of this thesis is that we have produced a methodology which can provide a formal linkage between a symbolic state enumeration system and a theorem proving system based on a verified symbolic state enumeration system. The methodology has been partly realized in two simplified version ..."
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The contribution of this thesis is that we have produced a methodology which can provide a formal linkage between a symbolic state enumeration system and a theorem proving system based on a verified symbolic state enumeration system. The methodology has been partly realized in two simplified versions of the MDG system
, Soene Tahar
"... cation Abstract. We describe a hybrid formal hardware verication tool that links the HOL interactive proof system and the MDG automated hardware verication tool. It supports a hierarchical verication approach that mirrors the hierarchical structure of designs. We obtain advantages of both vericat ..."
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cation Abstract. We describe a hybrid formal hardware verication tool that links the HOL interactive proof system and the MDG automated hardware verication tool. It supports a hierarchical verication approach that mirrors the hierarchical structure of designs. We obtain advantages of both verication paradigms. We illustrate its use by considering a component of a communications chip. Verication with the hybrid tool is signicantly faster and more tractable than using either tool alone. 1
, Soene Tahar
"... Abstract. An existential theorem, for the specication or implementation of hardware, states that for any inputs there must exist at least one output which is consistent with it. It is proved to prevent an inconsistent model being produced and it is required to formally import the verication result ..."
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Abstract. An existential theorem, for the specication or implementation of hardware, states that for any inputs there must exist at least one output which is consistent with it. It is proved to prevent an inconsistent model being produced and it is required to formally import the verication result from one verication system to another system. In this paper, we investigate the verication of the existential theorems of hardware specications and implementations. Whilst much of the approach is generally applicable, we specically consider a hybrid system linking the MDG hardware verication system with the HOL interactive proof system. We investigate existential theorems based on the syntax and semantics of the MDG input language (MDGHDL) in HOL. We de ne an output representation for each component in the MDGHDL component library. We summarize a general method which is used to prove the existential theorem for any MDGHDL program. The method can also be used to solve other existentially quantied goals. 1