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PerformanceOriented Placement and Routing for FieldProgrammable Gate Arrays
, 1995
"... This paper presents a performanceoriented placement and routing tool for fieldprogrammable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graphbased strategy for detailed routing, our tool optimizes sourcesink pathlengths, channel width an ..."
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Cited by 20 (5 self)
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This paper presents a performanceoriented placement and routing tool for fieldprogrammable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graphbased strategy for detailed routing, our tool optimizes sourcesink pathlengths, channel width and total wirelength. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route a number of industrial benchmarks. 1 Introduction Fieldprogrammable gate arrays, or FPGAs, afford designers a versatile and inexpensive way to implement and test VLSI designs [5, 10]. FPGAs are available in a number of styles and configurations [29]. One of the most common FPGA architectures consists of symmetrical arrays of userconfigurable logic blocks interconnected by a set of programmable routing resources [32] (Figure 1). FPGA reprogrammability is achieved at the expense of performance, i.e., long signal delays through the reconfigurab...
Spanning Trees in Hypergraphs with Applications to Steiner Trees
, 1998
"... This dissertation examines the geometric Steiner tree problem: given a set of terminals in the plane, find a minimumlength interconnection of those terminals according to some geometric distance metric. In the process, however, it addresses a much more general and widely applicable problem, that of ..."
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Cited by 19 (1 self)
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This dissertation examines the geometric Steiner tree problem: given a set of terminals in the plane, find a minimumlength interconnection of those terminals according to some geometric distance metric. In the process, however, it addresses a much more general and widely applicable problem, that of finding a minimumweight spanning tree in a hypergraph. The geometric Steiner tree problem is known to be NPcomplete for the rectilinear metric, and NPhard for the Euclidean metric. The fastest exact algorithms (in practice) for these problems use two phases: First a small but sufficient set of full Steiner trees (FSTs) is generated and then a Steiner minimal tree is constructed from this set. These phases are called FST generation and FST concatenation, respectively, and an overview of each phase is presented. FST concatenation is almost always the most expensive phase, and has traditionally been accomplished via simple backtrack search or dynamic programming.
A New Exact Algorithm for Rectilinear Steiner Trees
 IN INTERNATIONAL SYMPOSIUM ON MATHEMATICAL PROGRAMMING
, 1997
"... Given a finite set V of points in the plane (called terminals), the rectilinear Steiner minimal tree is a shortest network of horizontal and vertical lines connecting all the terminals of V . The decision form of this problem has been shown to be NPcomplete [8]. A new algorithm is presented that ..."
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Cited by 15 (1 self)
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Given a finite set V of points in the plane (called terminals), the rectilinear Steiner minimal tree is a shortest network of horizontal and vertical lines connecting all the terminals of V . The decision form of this problem has been shown to be NPcomplete [8]. A new algorithm is presented that computes provably optimal Steiner trees using the "FST concatenation" approach. In the "FST generation" phase, extensive geometric processing is used to identify a set of full Steiner trees (FSTs). In the subsequent FST concatenation phase, a Steiner minimal tree is then constructed by a finding a minimal spanning subset of the FSTs. This FST concatenation approach has been more efficient in practice than all other methods currently known. In previous work [19], [20] the author used problem decomposition methods and a "dumb" backtrack search to concatenate FSTs, solving problem instances with up to 65 terminals. Most 45 point instances could be solved within one CPU day on a worksta...
Placement and Routing for ThreeDimensional FPGAs
, 1996
"... We explore physical layout for a threedimensional (3D) FPGA architecture. For placement, we introduce a topdown partitioning technique based on rectilinear Steiner trees; we then employ a onestep router to produce the final layout. Experimental results indicate that our approach produces effective ..."
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Cited by 14 (2 self)
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We explore physical layout for a threedimensional (3D) FPGA architecture. For placement, we introduce a topdown partitioning technique based on rectilinear Steiner trees; we then employ a onestep router to produce the final layout. Experimental results indicate that our approach produces effective 3D layouts, using considerably shorter average interconnect distance than is achievable with conventional 2D FPGA's of comparable size. 1 Introduction A fieldprogrammable gate array (FPGA) is a flexible and reusable design alternative to custom integrated circuits. Using FPGAs, digital designs can be quickly implemented and emulated in hardware, which enables a faster, more economical design cycle [8]. The flexible logic and connection resources of FPGAs allow different designs to be implemented on the same hardware. However, this versatility comes at the expense of a substantial performance penalty due primarily to signal delay through the programmable routing switches. This delay can a...
Computing Optimal Rectilinear Steiner Trees: A Survey and Experimental Evaluation
 Discrete Applied Mathematics
, 1998
"... The rectilinear Steiner tree problem is to find a minimumlength rectilinear interconnection of a set of points in the plane. A reduction from the rectilinear Steiner tree problem to the graph Steiner tree problem allows the use of exact algorithms for the graph Steiner tree problem to solve the rec ..."
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Cited by 13 (2 self)
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The rectilinear Steiner tree problem is to find a minimumlength rectilinear interconnection of a set of points in the plane. A reduction from the rectilinear Steiner tree problem to the graph Steiner tree problem allows the use of exact algorithms for the graph Steiner tree problem to solve the rectilinear problem. Furthermore, anumber of more direct, geometric algorithms have been devised for computing optimal rectilinear Steiner trees. This paper surveys algorithms for computing optimal rectilinear Steiner trees and presents experimental results comparing nine of them: graph Steiner tree algorithms due to Beasley, Bern, Dreyfus and Wagner, Hakimi, and Shore, Foulds, and Gibbons and geometric algorithms due to Ganley and Cohoon, Salowe and Warme, and Thomborson, Alpern, and Carter. 1 Introduction The rectilinear Steiner tree (RST) problem is stated as follows: given a set T of n points called terminals in the plane, find a set S of additional points called Steiner points such tha...
A Spiffy Tool for the Simultaneous Placement and Global Routing of ThreeDimensional Field Programmable Gate Arrays
 Ninth Great Lakes Symposium on VLSI
, 1999
"... FPGAs are a useful and flexible alternative to custom design chips, but can suffer from severe interconnection delay. The 3DFPGA is an alternative to the twodimensional architecture that has been proposed to reduce these delay problems [2]. Here we present Spiffy – the first tool specifically desi ..."
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Cited by 7 (3 self)
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FPGAs are a useful and flexible alternative to custom design chips, but can suffer from severe interconnection delay. The 3DFPGA is an alternative to the twodimensional architecture that has been proposed to reduce these delay problems [2]. Here we present Spiffy – the first tool specifically designed for the placement and global routing of 3DFPGAs. Spiffy produces some of the best results in the literature, and using Spiffy we can show that when mapped to the 3DFPGA architecture, circuits tend to have considerably shorter netlength, making this new chip an improvement over the standard architecture. 1
Provably Good Moat Routing
, 1998
"... Moat routing is the routing of nets between the input/output pads and the core circuit. In this paper, it is proved that moat routing is NPcomplete under the routing model in which there are no vertical conflicts and doglegs are disallowed (i.e., every net is routed within a single track). This con ..."
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Cited by 1 (1 self)
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Moat routing is the routing of nets between the input/output pads and the core circuit. In this paper, it is proved that moat routing is NPcomplete under the routing model in which there are no vertical conflicts and doglegs are disallowed (i.e., every net is routed within a single track). This contrasts with the fact that channel routing is efficiently solvable under these restrictions. The paper then presents an approximation algorithm for moat routing that computes moat routing solutions that are guaranteed to use at most three times the optimal number of tracks. Empirical results are presented indicating that for a number of industrial benchmarks, the algorithm produces solutions that are near optimal and that use significantly fewer tracks than previous moat routing strategies. Keywords: Approximation algorithms, computational complexity, moat routing. 1 Introduction The final stage in detailed routing is typically to route the connections between the input/output pads and the...
Fast Heuristic Techniques for FPGA Placement based on Multilevel Clustering
, 2003
"... I hereby declare that I am the sole author of this thesis. I authorize the University of Guelph to lend this thesis to other institutions or individuals for the purpose of scholarly research. I further authorize the University of Guelph to reproduce this thesis by photocopying or by other means, in ..."
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Cited by 1 (1 self)
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I hereby declare that I am the sole author of this thesis. I authorize the University of Guelph to lend this thesis to other institutions or individuals for the purpose of scholarly research. I further authorize the University of Guelph to reproduce this thesis by photocopying or by other means, in total or in part, at the request of other institutions or individuals for the purpose of scholarly research. ii The University of Guelph requires the signatures of all persons using or photocopying this thesis. Please sign below, and give address and date. iii FieldProgrammable Gate Arrays (FPGAs) are semiconductor chips that can realize most digital circuits on site by specifying programmable logic and their interconnections. The use of FPGAs has grown almost exponentially because they dramatically reduce design turnaround time and startup cost for electronic products compared with traditional
On Approximation of the Powerp and Bottleneck Steiner Trees
, 1998
"... Many VLSI routing applications, as well as the facility location problem involve computation of Steiner trees with nonlinear cost measures. We consider two most frequent versions of this problem. In the powerp Steiner problem the the cost is defined as the sum of the edge length raised to power p, ..."
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Many VLSI routing applications, as well as the facility location problem involve computation of Steiner trees with nonlinear cost measures. We consider two most frequent versions of this problem. In the powerp Steiner problem the the cost is defined as the sum of the edge length raised to power p, while in the bottleneck Steiner problem the cost is the maximum of the edge lengths. In contrast to the classical Steiner problem, the objective of the powerp and bottleneck Steiner tree problems is to minimize the sum of the edge lengths raised to the p power or the maximum edge length, respectively. We show that the both problems are NPhard and, moreover, the bottleneck Steiner trees cannot be approximated with the factor less than 2, unless P = NP. We prove that the minimum spanning tree only constant times worse than the powerp Steiner tree in any metric space. In particular, for p = 2, we show that the minimum spanning tree is at most 23.3 times worse than the optimum and construct...
Algorithmic and Theoretical Problems Related to the Physical Design of Three Dimensional Field Programmable Gate Arrays
, 2000
"... Field Programmable Gate Arrays (FPGAs) have become an increasingly useful and important architecture in hardware design. As a flexible alternative to custom integrated chips, FPGAimplemented designs can be produced quickly and cheaply. However, this flexibility comes at a significant performance pe ..."
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Field Programmable Gate Arrays (FPGAs) have become an increasingly useful and important architecture in hardware design. As a flexible alternative to custom integrated chips, FPGAimplemented designs can be produced quickly and cheaply. However, this flexibility comes at a significant performance penalty. To help address this issue, we propose a family of threedimensional FPGA architectures, with increased speed and smaller size as compared to existing 2D FPGAs. We implemented the first suite of tools for creating circuit designs for the new proposed architecture, and used these tools to demonstrate the efficacy of 3D FPGAs (e.g., 3D FPGA circuit mappings seem superior to those mapped to 2D ones). We explored several issues arising in the design of both 2D and 3D FPGAs, and implemented two useful tools: (1) Spiffy, which performs placement and global routing simultaneously for 2D and 3D FPGAs, and (2) Gambit, which is the first tool to perform placement, global routing and detailed routing simultaneously, and which demonstrates the usefulness of conflict graphs. These tools yield superior solutions within reasonable runtimes, and employ a "template smoothing" technique which significantly improves the results at a modest runtime cost. Our results indicate that 3D FPGAs are a viable future architecture.