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12
Scheduling And Behavioral Transformations For Parallel Systems
, 1993
"... In a parallel system, either a VLSI architecture in hardware or a parallel program in software, the quality of the final design depends on the ability of a synthesis system to exploit the parallelism hidden in the input description of applications. Since iterative or recursive algorithms are usually ..."
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Cited by 39 (3 self)
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In a parallel system, either a VLSI architecture in hardware or a parallel program in software, the quality of the final design depends on the ability of a synthesis system to exploit the parallelism hidden in the input description of applications. Since iterative or recursive algorithms are usually the most timecritical parts of an application, the parallelism embedded in the repetitive pattern of an iterative algorithm needs to be explored. This thesis studies techniques and algorithms to expose the parallelism in an iterative algorithm so that the designer can find an implementation achieving a desired execution rate. In particular, the objective is to find an efficient schedule to be executed iteratively. A form of dataflow graphs is used to model the iterative part of an application, e.g. a digital signal filter or the while/for loop of a program. Nodes in the graph represent operations to be performed and edges represent both intraiteration and interiteration precedence relat...
Optimal FPGA Mapping and Retiming with Efficient Initial State Computation
 IEEE Trans. CAD
, 1998
"... Retiming is a well known technique for sequential circuit optimization originally proposed by Leiserson and Saxe [LeRS83, LeSa91]. For designs with given initial states, however, new equivalent initial states must be computed for retiming, which unfortunately is NPhard. In this paper we propose a n ..."
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Cited by 16 (0 self)
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Retiming is a well known technique for sequential circuit optimization originally proposed by Leiserson and Saxe [LeRS83, LeSa91]. For designs with given initial states, however, new equivalent initial states must be computed for retiming, which unfortunately is NPhard. In this paper we propose a novel polynomial time algorithm for optimal FPGA mapping with forward retiming to minimize the clock period with guaranteed initial state computation. It enables a new methodology of separating forward retiming from backward retiming to avoid timeconsuming iterations between retiming and initial state computation. Comparing with the clock period computed by our algorithm, the clock period by conventional approaches of separate mapping followed by retiming [CoDi94, LeSa91] is 20.2% larger, but the clock period by recent approaches of optimal mapping with retiming [PaLi96, PaLi99, CoWu96a] is 2.8% smaller. However, many of the optimal mapping with retiming solutions by [PaLi96, PaLi99, CoWu96a] cannot compute an equivalent initial state by SIS [SeSL92] based on the stateoftheart algorithm of equivalent initial state computation for retiming in [ToBr93]. Our approach is also applicable to circuits with partial initial state assignment. 1
Sequential Circuit Delay Optimization Using Global Path Delays
 In 30th ACM/IEEE Design Automation Conference
, 1993
"... ABSTRACT: We propose a novel sequential delay optimization technique based on network flow methods that simultaneously exploits delays on all paths in the circuit. We view the sequential circuit as an interconnection of path segments with prespecified delays. Path segments are bounded by flipflo ..."
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Cited by 9 (0 self)
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ABSTRACT: We propose a novel sequential delay optimization technique based on network flow methods that simultaneously exploits delays on all paths in the circuit. We view the sequential circuit as an interconnection of path segments with prespecified delays. Path segments are bounded by flipflops, primary inputs or primary outputs. Recognizing that a delay optimizer can satisfy certain delay constraints more easily than others, we first propose a measure of difficulty for the delay optimizer. Our measure is based on explicit path delays to be satisfied by the delay optimizer. Also, our measure induces a partial order on the set of possible delay constraints. We then compute a set of delay constraints that is optimal with respect to our measure. The delay constraint set is optimal in the sense that it is the easiest constraint that can be specified to the delay optimizer. We formulate the delay constraint calculation problem as a minimum cost network flow problem. If the delay optimizer satisfies the optimal delay constraint set, then the resynthesized circuit may have several pat hs exceeding the desired clock period. However, we show that the resynthesized circuit can always be retimed to achieve the desired clock period. Experimental results on MCNC synthesis benchmarks show that our method improves the performance of circuits beyond what is achievable using optimal retiming and conventional combinational logic synthesis. 1.
Optimal wire retiming without binary search
 In Proc. Intl. Conf. on ComputerAided Design
, 2004
"... Abstract—The problem of retiming over a netlist of macroblocks to achieve minimal clock period, where block internal structures may not be changed and flipflops may not be inserted on some wire segments, is called the optimal wire retiming problem. This paper presents a new algorithm that solves th ..."
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Cited by 8 (1 self)
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Abstract—The problem of retiming over a netlist of macroblocks to achieve minimal clock period, where block internal structures may not be changed and flipflops may not be inserted on some wire segments, is called the optimal wire retiming problem. This paper presents a new algorithm that solves the optimal wire retiming problem with polynomialtime worst case complexity. Since the new algorithm avoids binary search and is essentially incremental, it has the potential of being combined with other optimization techniques. Experimental results show that the new algorithm is very efficient in practice. Index Terms—Algorithms, circuit modeling, circuit optimization, design methodology, interconnects, pipelining, polynomial complexity, retiming. I.
PotentialDriven Statistical Ordering of Transformations
, 1997
"... Successive, well organized application of transformations has been widely recognized as an exceptionally effective, but complex and difficult CAD task. We introduce a new potentialdriven statistical approach for ordering transformations. Two new synthesis ideas are the backbone of the approach. The ..."
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Cited by 8 (5 self)
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Successive, well organized application of transformations has been widely recognized as an exceptionally effective, but complex and difficult CAD task. We introduce a new potentialdriven statistical approach for ordering transformations. Two new synthesis ideas are the backbone of the approach. The first idea is to quantify the characteristics of all transformations and the relationship between them based on their potential to reorganize a computation such that the complexity of the corresponding implementation is reduced. The second one is based on the observation that transformations may disable each other not only because they prevent the application of the other transformation, but also because both transformations target the same potential of the computation. These two observations drastically reduce the search space to find efficient and effective scripts for ordering transformations. A key algorithmic novelty is that both conceptual and optimization insights as well as all opti...
Effects of Resource Sharing on Circuit Delay: An Assignment Algorithm for Clock Period Optimization
"... This paper analyzes the effect of resource sharing and assignment on the clock period of the synthesized circuit. The assignment phase assigns or binds operations of the scheduled behavioral description to a set of allocated resources. We focus on controlflow intensive descriptions, characterized ..."
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Cited by 3 (0 self)
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This paper analyzes the effect of resource sharing and assignment on the clock period of the synthesized circuit. The assignment phase assigns or binds operations of the scheduled behavioral description to a set of allocated resources. We focus on controlflow intensive descriptions, characterized by the presence of mutually exclusive paths due to the presence of nested conditional branches and loops. We show that
Behavioral Level Guidance Using PropertyBased Design Characterization by
, 1996
"... BehavioralLevel Guidance Using PropertyBased Design Lisa Marie Guerra Doctor of Philosophy in Engineering  Electrical Engineering and Computer Sciences University of California at Berkeley Professor Jan M. Rabaey, Chair The growing importance of optimization, short time to market windows ..."
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Cited by 2 (0 self)
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BehavioralLevel Guidance Using PropertyBased Design Lisa Marie Guerra Doctor of Philosophy in Engineering  Electrical Engineering and Computer Sciences University of California at Berkeley Professor Jan M. Rabaey, Chair The growing importance of optimization, short time to market windows, and exponentially growing design complexity are just a few of the factors shaping the stateoftheart synthesis process. In particular, optimization at the early stages of design is crucial  at the system and behavioral levels, orders of magnitude performance improvement in key design metrics such as throughput, power, and area can be attained. This requires, however, strategic and coordinated application of design techniques best suited for a target design. The problem, however, is the number of options currently available is overwhelming, and as a result, design exploration is often conducted in a qualitative, adhoc manner.
Sequential Logic Optimization with Implicit Retiming and Resynthesis
, 1996
"... This paper introduces a new logic transformation that integrates retiming with algebraic and Boolean transformations at the technologyindependent level. It offers an additional degree of freedom in sequential network optimization resulting from implicit retiming across logic blocks and fanout stem ..."
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Cited by 2 (1 self)
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This paper introduces a new logic transformation that integrates retiming with algebraic and Boolean transformations at the technologyindependent level. It offers an additional degree of freedom in sequential network optimization resulting from implicit retiming across logic blocks and fanout stems. The application of this transformation to sequential network synthesis results in the optimization of logic across register boundaries. We have implemented our new technique within the SIS framework and demonstrated its effectiveness in terms of cycletime minimization on a set of sequential benchmark circuits. Keywords Sequential Logic Synthesis, Logic Optimization, Retiming 1 INTRODUCTION Over the years, sequential circuit synthesis has been a subject of intensive investigation. Though synthesis of combinational logic has attained a significant level of maturity, sequential circuit synthesis is lagging behind. In current state of affairs, sequential networks are first optimized by ap...
THE RETIMING AND ROUTING OF VLSI CIRCUITS
, 1998
"... In this thesis, we explore three problems arising during the logic synthesis and physical design stages of VLSI circuit design. We rst present a new formulation for the retiming of singlephase clocked circuits containing latches. Then, we discuss crosstalk optimization in channelbased routings, a ..."
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Cited by 2 (2 self)
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In this thesis, we explore three problems arising during the logic synthesis and physical design stages of VLSI circuit design. We rst present a new formulation for the retiming of singlephase clocked circuits containing latches. Then, we discuss crosstalk optimization in channelbased routings, and nally present a new performancedriven algorithm for the layer assignment of critical global nets. Although singlephase clocked circuits containing latches are in widespread use, there is no existing practical formulation for such circuits that allows retimingbased optimizations. We present anovel, ILPbased formulation for the retiming of such circuits. This formulation can be used to optimize any linearizable objective function. As examples, we discuss the optimization of the clock period and the area of such circuits. Our experiments demonstrate that our approach ise cient and generates ILPs that are easy to solve. We address the increased importance of crosstalk avoidance in deep sub
Optimizing Circuits with Confidence Probability Using Probabilistic Retiming
 In Proceedings of the 1998 International Symposium onCircuits and Systems
, 1998
"... VLSI circuit manufacturing results in theoretically identical components that actually have varying propagation delays. A "worstcase " or even "averagecase" estimation of such delays during the design procedure may be overly pessimistic and will lead to costly and unnecessary redesign cycles. This ..."
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Cited by 2 (0 self)
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VLSI circuit manufacturing results in theoretically identical components that actually have varying propagation delays. A "worstcase " or even "averagecase" estimation of such delays during the design procedure may be overly pessimistic and will lead to costly and unnecessary redesign cycles. This paper presents a new optimization methodology, called probabilistic retiming, which transforms a circuit based on statistical timing data gathered either from component production histories or from a simulation of the fabrication process. Such circuits are modeled as graphs where each vertex represents a combinational element that has a probabilistic timing characteristic. A polynomialtime algorithm, applicable to such a graph, is developed which retimes a circuit in order to produce a design operating in a specified cycle time within a given confidence level. Experiments show that probabilistic retiming consistently produces faster circuits for a given confidence level, as compared with th...