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16
An interiorpoint method for largescale l1regularized logistic regression
 Journal of Machine Learning Research
, 2007
"... Logistic regression with ℓ1 regularization has been proposed as a promising method for feature selection in classification problems. In this paper we describe an efficient interiorpoint method for solving largescale ℓ1regularized logistic regression problems. Small problems with up to a thousand ..."
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Cited by 167 (5 self)
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Logistic regression with ℓ1 regularization has been proposed as a promising method for feature selection in classification problems. In this paper we describe an efficient interiorpoint method for solving largescale ℓ1regularized logistic regression problems. Small problems with up to a thousand or so features and examples can be solved in seconds on a PC; medium sized problems, with tens of thousands of features and examples, can be solved in tens of seconds (assuming some sparsity in the data). A variation on the basic method, that uses a preconditioned conjugate gradient method to compute the search step, can solve very large problems, with a million features and examples (e.g., the 20 Newsgroups data set), in a few minutes, on a PC. Using warmstart techniques, a good approximation of the entire regularization path can be computed much more efficiently than by solving a family of problems independently.
ℓ1 Trend Filtering
, 2007
"... The problem of estimating underlying trends in time series data arises in a variety of disciplines. In this paper we propose a variation on HodrickPrescott (HP) filtering, a widely used method for trend estimation. The proposed ℓ1 trend filtering method substitutes a sum of absolute values (i.e., ..."
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Cited by 22 (5 self)
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The problem of estimating underlying trends in time series data arises in a variety of disciplines. In this paper we propose a variation on HodrickPrescott (HP) filtering, a widely used method for trend estimation. The proposed ℓ1 trend filtering method substitutes a sum of absolute values (i.e., an ℓ1norm) for the sum of squares used in HP filtering to penalize variations in the estimated trend. The ℓ1 trend filtering method produces trend estimates that are piecewise linear, and therefore is well suited to analyzing time series with an underlying piecewise linear trend. The kinks, knots, or changes in slope, of the estimated trend can be interpreted as abrupt changes or events in the underlying dynamics of the time series. Using specialized interiorpoint methods, ℓ1 trend filtering can be carried out with not much more effort than HP filtering; in particular, the number of arithmetic operations required grows linearly with the number of data points. We describe the method and some of its basic properties, and give some illustrative examples. We show how the method is related to ℓ1 regularization based methods in sparse signal recovery and feature selection, and list some extensions of the basic method.
Minimizing effective resistance of a graph
 SIAM Review
, 2005
"... Abstract. The effective resistance between two nodes of a weighted graph is the electrical resistance seen between the nodes of a resistor network with branch conductances given by the edge weights. The effective resistance comes up in many applications and fields in addition to electrical network a ..."
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Abstract. The effective resistance between two nodes of a weighted graph is the electrical resistance seen between the nodes of a resistor network with branch conductances given by the edge weights. The effective resistance comes up in many applications and fields in addition to electrical network analysis, including, for example, Markov chains and continuoustime averaging networks. In this paper we study the problem of allocating edge weights on a given graph in order to minimize the total effective resistance, i.e., the sum of the resistances between all pairs of nodes. We show that this is a convex optimization problem, and can be solved efficiently either numerically, or, in some cases, analytically. We show that optimal allocation of the edge weights can reduce the total effective resistance of the graph (compared to uniform weights) by a factor that grows unboundedly with the size of the graph. We show that among all graphs with n nodes, the path has the largest value of optimal total effective resistance, and the complete graph the least. 1. Introduction. Let N be a network with n nodes and m edges, i.e., an undirected graph (V, E) with V  = n, E  = m, and nonnegative weights on the edges. We call the weight on edge l its conductance, and denote it by gl. The effective resistance between a pair of nodes i and j, denoted Rij, is the electrical resistance measured across nodes i and j, when the network represents an electrical circuit with each edge (or branch, in the terminology of electrical circuits) a resistor with (electrical) conductance gl. In other
The YArchitecture for onchip interconnect: Analysis and methodology
 Analysis and Methodology”, Proc. Int. Conf. Computer Aided Design
, 2003
"... The Yarchitecture for onchip interconnect is based on pervasive use of 0, 120, and 240degree oriented semiglobal and global wiring. Its use of three uniform directions exploits onchip routing resources more efficiently than traditional Manhattan wiring architecture. This paper gives indepth ..."
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Cited by 16 (2 self)
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The Yarchitecture for onchip interconnect is based on pervasive use of 0, 120, and 240degree oriented semiglobal and global wiring. Its use of three uniform directions exploits onchip routing resources more efficiently than traditional Manhattan wiring architecture. This paper gives indepth analysis of deployment issues associated with the Yarchitecture. Our contributions are as follows: (1) We analyze communication capability (throughput of meshes) for different interconnect architectures using a multicommodity flow approach and a Rentian communication model. Throughput of the Yarchitecture is largely improved compared to the Manhattan architecture, and is close to the throughput of the Xarchitecture. (2) We improve existing estimates for the wirelength reduction of various interconnect architectures by taking into account the effect of routinggeometryaware placement. (3) We propose a symmetrical Y clock tree structure with better total wire length compared to both H and X clock tree structures, and better path length compared to the H tree. (4) We discuss power distribution under the Yarchitecture, and give analytical and SPICE simulation results showing that the power network in Yarchitecture can achieve 8.5 % less IR drop than an equallyresourced power network in Manhattan architecture. (5) We propose the use of via tunnels and banks of via tunnels as
Analysis and Optimization of Structured Power/Ground Networks
 IEEE Trans. Computeraided Design
, 2003
"... This paper presents an efficient method for optimizing power/ground (P/G) networks by widening wires and adding decoupling capacitors (decaps). It proposes a structured skeleton that is intermediate to the conventional method that uses full meshes which are hard to analyze efficiently, and treestru ..."
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Cited by 7 (0 self)
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This paper presents an efficient method for optimizing power/ground (P/G) networks by widening wires and adding decoupling capacitors (decaps). It proposes a structured skeleton that is intermediate to the conventional method that uses full meshes which are hard to analyze efficiently, and treestructured networks, which provide poor performance. As an example, we consider a P/G network structure modeled as an overlying mesh with underlying trees originating from the mesh, which eases the task of analysis with acceptable performance sacrifices. A fast and efficient eventdriven P/G network simulator is proposed, which hierarchically simulates the P/G network with an adaptation of PRIMA to handle nonzero initial conditions. An adjoint network that incorporates the variable topology of the original P/G network, as elements switch in and out of the network, is constructed to calculate the transient adjoint sensitivity over multiple intervals. The gradients of the most critical node with respect to each wire width and decap are used by a sensitivitybased heuristic optimizer that minimizes a weighted sum of the wire and the decap area. Experimental results show that this procedure can be used to efficiently optimize large networks. I.
Genetic Network Identification Using Convex Programming
, 2007
"... Gene regulatory networks capture interactions between genes and other cell substances, resulting in various models for the fundamental biological process of transcription and translation. The expression levels of the genes are typically measured as mRNA concentration in microarray experiments. In ..."
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Gene regulatory networks capture interactions between genes and other cell substances, resulting in various models for the fundamental biological process of transcription and translation. The expression levels of the genes are typically measured as mRNA concentration in microarray experiments. In a so called genetic perturbation experiment, small perturbations are applied to equilibrium states and the resulting changes in expression activity are measured. One of the most important problems in systems biology is to use these data to identify the interaction pattern between genes in a regulatory network, especially in a large scale network. In this paper, we develop a novel algorithm for identifying the smallest genetic network that explains genetic perturbation experimental data. By construction, our identification algorithm is able to incorporate and respect any a priori knowledge known about the network structure. A priori biological knowledge is typically qualitative, encoding whether one gene affects another gene or not, or whether the effect is positive or negative. Our method is based on a convex programming relaxation of the combinatorially hard problem of L0 minimization, so it can efficiently handle large scale problems. We apply the proposed method to the identification of a subnetwork of the SOS pathway in Escherichia coli, the segmentation polarity network in Drosophila melanogaster, and a larger artificial network for measuring the performance of the method. In all cases, we show that our method performs better than prior methods.
AllDigital RingOscillatorBased Macro for Sensing Dynamic Supply Noise Waveform
 IEEE Journal of SolidState Circuits
, 2009
"... Abstract—This paper proposes an alldigital measurement circuit called a “gated oscillator ” to capture the waveforms of dynamic power supply noise. An improved gated oscillator with a powergating structure is also proposed. The gated oscillator is constructed using standard cells, and thus is easi ..."
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Abstract—This paper proposes an alldigital measurement circuit called a “gated oscillator ” to capture the waveforms of dynamic power supply noise. An improved gated oscillator with a powergating structure is also proposed. The gated oscillator is constructed using standard cells, and thus is easily embedded in SoCs. Its performance was evaluated using test chips fabricated in a 90 nm process. The gated oscillator achieved 5.3–5.9 Gsample/s with an area of 10.08 6.72 m2, and the improved power gating structure achieved 6.6–8.3 Gsample/s in a 90 nm process. The characteristics of the gated oscillator and related design issues are also discussed. These characteristics were verified on silicon. We evaluated the effect of the decoupling capacitance based on measurement results obtained using the gated oscillator, and demonstrated that it could be used to verify power integrity. Index Terms—Decoupling capacitance, measurement circuit, power supply noise, ring oscillator. I.
Simultaneous area minimization and decaps insertion for power delivery network using adjoint senstivity analysis with ieks method
 in Proc. of VLSI Design/CAD Symposium
, 2003
"... Abstract — The soaring clocking frequency and integration density demand robust and stable power delivery to support tens of millions of transistor switching. In this paper, we consider the problem of minimizing the area of wires and decoupling capacitors (decaps) for a power delivery network, subje ..."
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Abstract — The soaring clocking frequency and integration density demand robust and stable power delivery to support tens of millions of transistor switching. In this paper, we consider the problem of minimizing the area of wires and decoupling capacitors (decaps) for a power delivery network, subject to the limit on integral of voltage drops. First, we derive the gradients of constraint function without Tellegen’s theorem. This greatly simplifies the discuss of adjoint sensitivity analysis. Then, we apply the IEKS method to speed up the sensitivity analysis over 3 times. Finally, this efficient analyzer is incorporated with the stateoftheart nonlinear programming package, SNOPT, to perform the optimization. Extensive experimental results show that the proposed method can work efficiently for large power delivery networks. I.
ABSTRACT PowerDelivery Networks Optimization with Thermal Reliability Integrity ∗
"... With the growing power consumption in modern high performance VLSI designs, nonuniform temperature distribution and limited heatconduction capability have caused thermal induced performance and reliability degradation. Electromigration is the main reliability concern and will become a more limiting ..."
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With the growing power consumption in modern high performance VLSI designs, nonuniform temperature distribution and limited heatconduction capability have caused thermal induced performance and reliability degradation. Electromigration is the main reliability concern and will become a more limiting factor of IC designs. It must be addressed together with a thermal reliability modeling. This issue also has been recognized in the International Technology Roadmap for Semiconductors (ITRS) 2002 update as one of the difficult challenges [1]. Although the impacts of thermal effects on transistor and interconnect performance are wellstudied, but still how thermal effects affect the reliability of power delivery is not very clear. As a result, traditional powerdelivery designs without thermal consideration may cause softerror, reliability degradation, and even premature chip failures. In this paper, we propose an algorithm for powerdelivery networks optimization with thermal reliability integrity. By considering thermal and power integrity, we are able to achieve high power supply quality and thermal reliability. For a 56×72 mesh, our design shows that the lifetime of the optimized ground network is 9.8 years. Whereas the lifetime of the ground network designed by a traditional method without thermal integrity is only 4.1 years.
Integritydriven Power and Signal Network Codesign
"... Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wirelimited deep submicron designs. In this paper, we present a novel design methodology that simultaneously considers global signal routing ..."
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Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wirelimited deep submicron designs. In this paper, we present a novel design methodology that simultaneously considers global signal routing and power network design under integrity constraints. The key part to this approach is a simple yet accurate power net estimation formula that decides the minimum number of power nets needed to satisfy both power and signal integrity constraints prior to detailed layout. The proposed design methodology is a onepass solution to the codesign of power and signal networks in the sense that no iteration between them is required in order to meet design closure. Experiment results using large industrial benchmarks show that compared to the stateoftheart alternative design approach, the proposed method can reduce the power network area by 19.4% on average under the same signal and power integrity constraints with better routing quality, but use less runtime.