Results 1  10
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16
A cascaded sigmadelta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR
 IEEE Journal of SolidState Circuits
, 1997
"... Abstract — A lownoise multibit sigma–delta analogtodigital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient highresolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. ..."
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Abstract — A lownoise multibit sigma–delta analogtodigital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient highresolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16b implementation of the architecture, fabricated in a 0.6"m CMOS process, cascades a secondorder 5b sigma–delta modulator with a fourstage 12b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clockboosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25MHz signal bandwidth and a total harmonic distortion (THD) of 098 dB with a 100kHz input signal. Index Terms—Analogdigital conversion, bootstrapped switch, digital filters, dynamic element matching, pipeline processing, sigma–delta modulation, switched capacitor circuits. I.
Deterministic Analysis of Oversampled A/D Conversion and Sigma/Delta Modulation, and Decoding Improvements using Consistent Estimates
, 1993
"... Analogtodigital conversion (ADC) which consists in a double discretization of an analog signal in time and in amplitude is increasingly used in modern data acquisition. However, the conversion process always implies some loss of information due to amplitude quantization. Oversampling is the techni ..."
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Cited by 6 (0 self)
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Analogtodigital conversion (ADC) which consists in a double discretization of an analog signal in time and in amplitude is increasingly used in modern data acquisition. However, the conversion process always implies some loss of information due to amplitude quantization. Oversampling is the technique currently used to reduce this loss of accuracy. The error reduction can be performed by lowpass filtering the quantized signal, thus eliminating the high frequency components of the quantization error signal. This is the classical method used to reconstruct the analog signal from its oversampled and quantized version. This reconstruction scheme yields a mean squared error (MSE) inversely proportional to the oversampling ratio R. The fundamental question pursued in this thesis is the following: how much information is available in the oversampled and quantized version of a bandlimited signal for its reconstruction? In order to identify this information, it is essential to go back to the original description of quantization which is typically deterministic. We show that a reconstruction scheme fully takes this information into account
An approach to tackle quantization noise folding in doublesampling 61 modulation A/D converters
 IEEE Trans. Circuits Syst. II
, 2003
"... Abstract—61modulation is a proven method to realize high and very highresolution analogtodigital converters. A particularly efficient way to implement such a modulator uses doublesampling where the circuit operates during both clock phases of the masterclock. Hence, the sampling frequency is ..."
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Cited by 5 (4 self)
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Abstract—61modulation is a proven method to realize high and very highresolution analogtodigital converters. A particularly efficient way to implement such a modulator uses doublesampling where the circuit operates during both clock phases of the masterclock. Hence, the sampling frequency is twice the masterclock frequency. Unfortunately, path mismatch between both sampling branches causes a part of the quantization noise to fold from the Nyquist frequency back in the signal band. Therefore, the performance is severely degraded. In this paper, we show that the problem is reduced but not eliminated by employing multibit quantization. Next, we present an indepth solution for the problem. The approach consists of modifying the quantization noise transfer function of the overall modulator to have one or several zeros at the Nyquist frequency. This way the effect of noise folding can nearly be eliminated. It is shown that this can be implemented by a simple modification of one of the integrators of the overall modulator circuit. Finally, several design examples of singlebit and multibit modulators are discussed. Index Terms—Analogtodigital conversion, doublesampling, spectral shaping.
DeltaSigma Data Conversion in Wireless Transceivers
, 2002
"... Highperformance analogtodigital converters, digitaltoanalog converters, and fractional frequency synthesizers based on deltasigma (16) modulationcollectively referred to as data convertershave contributed significantly to the high level of integration seen in recent commercial wirel ..."
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Cited by 4 (2 self)
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Highperformance analogtodigital converters, digitaltoanalog converters, and fractional frequency synthesizers based on deltasigma (16) modulationcollectively referred to as data convertershave contributed significantly to the high level of integration seen in recent commercial wireless handset transceivers. This paper presents a tutorial on data converters and their uses and implications with respect to wireless transceiver architectures.
A Compensation Technique for SigmaDelta AnalogtoDigital Converters
 in Proceedings of the IEEE Instrumentation and Measurement Technology Conference
, 1997
"... This paper explores a compensation technique for mismatched amplifier gain and capacitor values in a three stage, third order noise shaping SigmaDelta analogtodigital converter (ADC). The paper concentrates on multistage noise shaping (MASH) architectures. Two possible sources of distortion are e ..."
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This paper explores a compensation technique for mismatched amplifier gain and capacitor values in a three stage, third order noise shaping SigmaDelta analogtodigital converter (ADC). The paper concentrates on multistage noise shaping (MASH) architectures. Two possible sources of distortion are examined and simulated. Using these simulation results, the distortion is identified, and a modified architecture is designed that attempts to compensate for these distortion terms. Simulation results show that the distortion caused by finite Opamp amplifier gains (all near 60 dB) may be reduced by over 13 dB over the operating band of the converter by using the modified architecture. I. Introduction The recent need for high resolution AnalogtoDigital Converters (ADCs) has forced the communications industry to research new radical designs to overcome the physical limitations of classic flash and other Nyquist rate converters. One of the new designs emerging as a candidate for low frequen...
A Low Oversampling Ratio 14b 500kHz ADC with a SelfCalibrated Multibit DAC
 IEEE J. SolidState Circuits
, 1996
"... Abstract — Deltasigma (16) analogtodigital converters (ADC’s) rely on oversampling to achieve highresolution. By applying multibit quantization to overcom stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14bit 500kHz 16 ADC is described t ..."
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Cited by 3 (0 self)
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Abstract — Deltasigma (16) analogtodigital converters (ADC’s) rely on oversampling to achieve highresolution. By applying multibit quantization to overcom stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14bit 500kHz 16 ADC is described that uses an oversampling ratio of only 16. A fourthorder embedded modulator, fourbit quantizer, and selfcalibrated digitaltoanalog converter (DAC) are used to achieve this performance. Although the highorder embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2"m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date. I.
Stable HighOrder DeltaSigma DACs
, 2003
"... Stability analysis of highorder deltasigma loops is a challenge. In this brief, a sufficient design criterion is presented for highorder multibit errorfeedback DACs which are especially suitable for highspeed operation. This analytical criterion might be too conservative, but it allows the desig ..."
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Cited by 1 (1 self)
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Stability analysis of highorder deltasigma loops is a challenge. In this brief, a sufficient design criterion is presented for highorder multibit errorfeedback DACs which are especially suitable for highspeed operation. This analytical criterion might be too conservative, but it allows the design of stable, robust, and highresolution deltasigma DACs. Both analytical and numerical analysis are performed for verification. Also, experimental results of a discretecomponent multiplierfree prototype demonstrate 10bit operation at a very low oversampling ratio of 4.
A Low Oversampling Ratio 14b 500kHz ΔΣ ADC with a SelfCalibrated Multibit DAC
"... Deltasigma (\Delta\Sigma) analogtodigital converters rely on oversampling technique to achieve highresolution. By overcoming stability limitations and applying multibit quantization, a circuit topology with greatly reduced oversampling requirements is developed. A 14bit 500 kHz deltasigma ADC ..."
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Cited by 1 (0 self)
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Deltasigma (\Delta\Sigma) analogtodigital converters rely on oversampling technique to achieve highresolution. By overcoming stability limitations and applying multibit quantization, a circuit topology with greatly reduced oversampling requirements is developed. A 14bit 500 kHz deltasigma ADC is described that uses an oversampling ratio of only 16. A fourthorder embedded modulator, fourbit quantizer, and selfcalibrated DAC are used to achieve this performance. Although the highorder embedded architecture was previously thought to be unstable, it is shown that with proper design a robust system can be obtained. Circuit design and implementation in a 1.2¯m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date. 1 Introduction Deltasigma (\Delta\Sigma) analogtodigital converters are well suited for low f...
New design criterion for highorder deltasigma DACs
"... This paper is a technical memorandum #3000121701091901 of Agere Systems ..."
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This paper is a technical memorandum #3000121701091901 of Agere Systems