Recently, various multibit noise-shaping digital-toanalog converters (DAC's) have been proposed that use digital signal processing techniques to cause the DAC noise arising from analog component mismatches to be spectrally shaped. Such DAC's have the potential to significantly increase the present precision limits of 16 data converters by eliminating the need for one-bit quantization in delta-sigma modulators. This paper extends the practicality of the noise-shaping DAC approach by presenting a general noise-shaping DAC architecture along with two special-case configurations that achieve first- and second-order noise-shaping, respectively. The second-order DAC configuration, in particular, is the least complex of those currently known to the author. Additionally, the paper provides a rigorous explanation of the apparent paradox of how the DAC noise can be spectrally shaped even though the sources of the DAC noise---the errors introduced by the analog circuitry---are not known to the ...

In this paper, the design procedure and practical issues regarding the realization of time-interleaved oversampling converters are presented. Using the concept of block digital filtering, it is shown that arbitrary 16 topologies can be converted into corresponding time-interleaved structures. Practical issues such as finite opamp gain, mismatching, and dc offsets are addressed, analyzed, and practical solutions to overcome some of these problems are discussed. To verify the theoretical results, a discrete-component prototype of a second-order time-interleaved 16 analog/digital (A/D) converter has been implemented and the design details as well as experimental results are presented. Index Terms---Converters, time-interleaved, oversampling. I. INTRODUCTION O VERSAMPLING converters have become a popular technique for data conversion [1]. One reason for their popularity is their outstanding linearity which comes from the fact that they usually exploit a 1-b quantizer. Even with a tr...

Abstract-We derive new properties of the single- and doubleloop sigma-delta modulators with constant inputs, by exploiting the inherent structure of the output sequences or codewords that the modulators are capable of producing. Specifically, we first derive upper bounds of O(.Y2) and O(-Y3) on the number of r-bit codewords for the single and double-loop modulators, respectively. We then derive analytical lower bounds on the mean squared error (MSE) obtainable by any decoder, linear or nonlinear, in approximating the constant input; based on.Y-bit codewords, the bounds are O(.Y-3) and O(AT-6) for the single and double-loop modulators, respectively. Optimal nonlinear decoders for constant inputs can be based on a table look-up approach which operates directly on the nonuniform quantization intervals. Numerical results show that if the constant input is uniformly distributed, the MSE of such nonlinear decoders are 0(-?*-3) and O(S-’) for the single- and doubleloop modulators, respectively. Using simulations we find that the optimal nonlinear decoders perform better than linear decoders, by about 3 and 20 dB for the single and double-loop modulators, respectively. We also introduce a cascade structure specifically for constant inputs, and derive its corresponding decoding algorithm. The idea behind the cascade structure is to requantize the residue from each stage in order to fully utilize the dynamic range of the next stage. We show that for a fixed latency, the MSE performance of our cascade structure is 12 dB superior, and its throughput is twice the conventional two-stage MASH modulator. I.

Analog-to-digital conversion (ADC) which consists in a double discretization of an analog signal in time and in amplitude is increasingly used in modern data acquisition. However, the conversion process always implies some loss of information due to amplitude quantization. Oversampling is the technique currently used to reduce this loss of accuracy. The error reduction can be performed by lowpass filtering the quantized signal, thus eliminating the high frequency components of the quantization error signal. This is the classical method used to reconstruct the analog signal from its oversampled and quantized version. This reconstruction scheme yields a mean squared error (MSE) inversely proportional to the oversampling ratio R. The fundamental question pursued in this thesis is the following: how much information is available in the oversampled and quantized version of a bandlimited signal for its reconstruction? In order to identify this information, it is essential to go back to the original description of quantization which is typically deterministic. We show that a reconstruction scheme fully takes this information into account

This research begins with reaction-diffusion, first proposed by Alan Turing in 1952 to account for morphogenesis -- the formation of hydranth tentacles, leopard spots, zebra stripes, etc. Reaction-diffusion systems have been researched primarily by biologists working on theories of natural pattern formation and by chemists modeling dynamics of oscillating reactions. The past few years have seen a new interest in reaction-diffusion spring up within the computer graphics and image processing communities. However, reaction-diffusion systems are generally unbounded, making them impractical for many applications. In this thesis we introduce a bounded and more flexible non-linear system, the "M-lattice", which preserves the natural pattern-formation properties of reaction-diffusion. On the theoretical front, we establish relationships between reaction-diffusion systems and paradigms in linear systems theory and certain types of artificial "neurally-inspired" systems. The M-lattice is closel...

Abstract — Delta-sigma (16) analog-to-digital converters (ADC’s) rely on oversampling to achieve high-resolution. By applying multibit quantization to overcom stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14-bit 500-kHz 16 ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-"m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date. I.

—In this paper we present a systematic method to scale the integrators output swings of modulator. It is shown that this scaling method preserves both the Noise Transfer Function and the Signal Transfer Function of the modulator. Examples are given to illustrate the effectiveness of the proposed method to alleviate circuit non-idealities.

High-performance analog-to-digital converters, digital-to-analog converters, and fractional- frequency synthesizers based on delta--sigma (16) modulation---collectively referred to as data converters---have contributed significantly to the high level of integration seen in recent commercial wireless handset transceivers. This paper presents a tutorial on data converters and their uses and implications with respect to wireless transceiver architectures.

Delta-sigma (\Delta\Sigma) analog-to-digital converters rely on oversampling technique to achieve high-resolution. By overcoming stability limitations and applying multibit quantization, a circuit topology with greatly reduced oversampling requirements is developed. A 14-bit 500 kHz delta-sigma ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated DAC are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design a robust system can be obtained. Circuit design and implementation in a 1.2-¯m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date. 1 Introduction Delta-sigma (\Delta\Sigma) analog-to-digital converters are well suited for low f...

Software radio architecture can support multiple standards by performing analog-to-digital (A/D) conversion of the radio frequency (RF) signals and running reconfigurable software programs on the backend digital signal processor (DSP). A slight variation of this architecture is the software defined radio architecture in which the A/D conversion is performed on intermediate frequency (IF) signals after a single down conversion. The first part of this research deals with the design and implementation of a fourth order continuous time bandpass sigma-delta (CT BP Σ∆) ADC based on LC filters for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC architecture is proposed which uses only non-return to zero feedback digital to analog converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining iii the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 µm SiGe