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Divide-and-Conquer Techniques for Global Throughput Optimization
- Proc. IEEE VLSI Signal Processing Workshop
, 1996
"... This paper proposes a divide-and-conquer approach for global throughput optimization which not only leverages upon existing techniques, but enables their more effective and coordinated use. The "divide" approach consists of logical partitioning of the computation into subparts falling into one of a ..."
Abstract
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Cited by 3 (2 self)
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This paper proposes a divide-and-conquer approach for global throughput optimization which not only leverages upon existing techniques, but enables their more effective and coordinated use. The "divide" approach consists of logical partitioning of the computation into subparts falling into one of a set of preclassified computation types. The subparts are then "conquered" through coordinated application of existing optimization techniques. We have characterized a set of techniques in terms of their expected effect on throughput, and can thus select the most promising techniques for each unique situation. The technique is not limited to a specific class of computations and gives higher, or at worst equal, improvement than previously reported techniques on all examples. 1.0 Introduction Throughput optimization techniques remain important for meeting the sampling rate requirements of modern DSP and communication applications. Though clock rates for ASICs and general purpose computing devi...
Behavioral Level Guidance Using Property-Based Design Characterization by
, 1996
"... Behavioral-Level Guidance Using Property-Based Design Lisa Marie Guerra Doctor of Philosophy in Engineering --- Electrical Engineering and Computer Sciences University of California at Berkeley Professor Jan M. Rabaey, Chair The growing importance of optimization, short time to market windows ..."
Abstract
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Cited by 2 (0 self)
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Behavioral-Level Guidance Using Property-Based Design Lisa Marie Guerra Doctor of Philosophy in Engineering --- Electrical Engineering and Computer Sciences University of California at Berkeley Professor Jan M. Rabaey, Chair The growing importance of optimization, short time to market windows, and exponentially growing design complexity are just a few of the factors shaping the state-of-the-art synthesis process. In particular, optimization at the early stages of design is crucial --- at the system and behavioral levels, orders of magnitude performance improvement in key design metrics such as throughput, power, and area can be attained. This requires, however, strategic and coordinated application of design techniques best suited for a target design. The problem, however, is the number of options currently available is overwhelming, and as a result, design exploration is often conducted in a qualitative, ad-hoc manner.

