A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach. Keywords--- Layout, Analog Design, Constraint-Driven Layout. I. Introduction The layout of analog circuits is intrinsically more difficult than the d...

New placement techniques are presented which substantially improve the process of automatic layout generation of analog IC's. Extremely tight specifications can be enforced on high-performance analog circuits by using simultaneous placement and module optimization. An algorithmic approach to module generation provides alternative sets of modules optimized with respect to area and performance but equivalent in terms of parasitics and topology. The final module selection is performed during the placement phase, based on Simulated Annealing. The flexibility of the annealing algorithm has been significantly improved, thus making it possible to more efficiently exploit the tradeoffs between area, parasitics and matching. 1 Introduction Layout design automation of analog IC's has seen considerable improvements in recent years despite a continuous increase of complexity and sophistication of analog and mixed-signal systems. On the one hand, denser and more advanced technologies have led to f...

Current technology allows for the integration of complete systems onto a single chip. These systems on chip (SoC) are increasingly designed by connecting together large pre-designed and verified modules, called cores, with the advantage being a faster design cycle. The development of third party Intellectual Property (IP) cores is a rapidly expanding industry, and whereas initially these were nearly all digital, analogue IP cores are now representing a greater proportion of this market. In this report we consider issues which should be addressed when designing analogue IP cores, from low-level circuit realisations to high level design methodologies. The switched current (SI) technique can implement analogue functions on the most basic of digital processes and further advantages of high speed and low voltage operation, suggest that this may be particularly suitable for implementing analogue IP cores. In this work, we have considered the design of analogue SI filter cores, these being a fundamental analogue building block. The wave filter design technique has been found particularly suitable as a filter design method as it is easily implemented in SI and the

This paper presents an optimization algorithm which simultaneously deals with the problems of placement and global routing in an analog macrocell layout style. The optimization process is based on a simulated annealing algorithm. We evaluate the physical placement of the cells and estimate the global routing for each intermediate solution generated. The basic idea, that together with an appropriate heuristic make the algorithm extremely efficient, consist of maintaining the same basic representative structure (slicing structures) for both problems. This method enables us to impose symmetry conditions and to penalize the existence of sensitive and noisy nets in the same channel.