Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of interconnect design as the technology feature size rapidly decreases towards below 0.1 micron. Then, we present commonly used interconnect models and a set of interconnect design and optimization techniques for improving interconnect performance and reliability. Finally, we present comparisons of different optimization techniques in terms of their efficiency and optimization results, and show the impact of these optimization techniques on interconnect performance in each technology generation from the 0.35µm to 0.07µm projected in the National Technology Roadmap for Semiconductors.

aggressors, we study switching pattern generation and switching time alignment that leads to worst-case crosstalk noise for a quiet victim or a noisy one. We assume that aggressors can have arbitrary switching patterns and can switch at arbitrary times. We show that the commonly used superposition algorithm results in 15% underestimation on average, and propose a new algorithm that has virtually the same complexity as the superposition algorithm but approximates the exhaustive search very well with only 4% underestimation on average. Further, we show that applying RC model to GHz+ interconnects in IRTS 0.10m technology underestimates crosstalk noise by up to 80%, and convincingly conclude that RLC model is necessary to analyze such interconnects.

Successful timing analysis of high-speed integrated circuits requires accurate delay computation. However, full-custom circuits popular in today’s CPU designs make this difficult. In this paper we introduce a symbolic method for computing the delay of these complex MOS circuits by modeling all devices as twoport networks. This approach allows us to handle various circuit structures, including series-parallel and arbitrary meshes, directly without the need to decompose them into simpler circuits first. In addition, the symbolic approach enables efficient computation of the delay as a function of its inputs and can naturally handle exclusivity conditions within the symbolic representation. 1.