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An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs
 in Proc. Int. Symp. on Physical Design
, 1997
"... In this paper, we formulated a new class of optimization problem, named the general CHposynomial program, which is more general than the simple and boundedvariation CHposynomial programs in [1]. We revealed the general dominance property so that an efficient and unified algorithm based on the loc ..."
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Cited by 7 (2 self)
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In this paper, we formulated a new class of optimization problem, named the general CHposynomial program, which is more general than the simple and boundedvariation CHposynomial programs in [1]. We revealed the general dominance property so that an efficient and unified algorithm based on the local refinement (LR) operation can be used to optimize the simple, boundedvariation and general CHposynomial programs. We applied the LRbased optimization algorithm to solve the device sizing problem using accurate tablebased model, and the wire sizing and spacing problem with consideration of coupling between multiple nets. Both problems are solved in the context of simultaneous device and wire sizing optimization for deep submicron designs. Experiments show that our LRbased optimization algorithm is very effective and extremely efficient. Up to 16.5% delay reduction is observed when compared with previous work based on the simple device model [1], and up to 31% delay reduction and 100x speedup is observed when compared the global interconnect sizing and spacing work [2]. We believe that our general CHposynomial formulation and LRbased algorithm can also be applied to other optimization problems in the CAD field.
Theory and Algorithm of LocalRefinement Based Optimization with Application to Device and Interconnect Sizing
, 1999
"... In this paper we formulate three classes of optimization problems: the simple, monotonicallyconstrained, and bounded CHprograms. We reveal the dominance property under the local refinement (LR) operation for the simple CHprogram, as well as the general dominance property under the pseudoLR opera ..."
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In this paper we formulate three classes of optimization problems: the simple, monotonicallyconstrained, and bounded CHprograms. We reveal the dominance property under the local refinement (LR) operation for the simple CHprogram, as well as the general dominance property under the pseudoLR operation for the monotonicallyconstrained CHprogram and the extendedLR operation for the bounded CHprogram. These properties enable a very efficient polynomialtime algorithm, using different types of LR operations to compute tight lower and upper bounds of the exact solution to any CHprogram. We show that the algorithm is capable of solving many layout optimization problems in deep submicron IC and/or highperformance MCM/PCB designs. In particular, we apply...
Theory and Algorithm of LocalRefinementBased Optimization with Application to Device and Interconnect Sizing
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 1999
"... In this paper we formulate three classes of optimization problems: the simple, monotonically constrained, and bounded CongHe (CH)programs. We reveal the dominance property under the local refinement (LR) operation for the simple CHprogram, as well as the general dominance property under the pseud ..."
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Cited by 7 (0 self)
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In this paper we formulate three classes of optimization problems: the simple, monotonically constrained, and bounded CongHe (CH)programs. We reveal the dominance property under the local refinement (LR) operation for the simple CHprogram, as well as the general dominance property under the pseudoLR operation for the monotonically constrained CHprogram and the extendedLR operation for the bounded CHprogram. These properties enable a very efficient polynomialtime algorithm, using different types of LR operations to compute tight lower and upper bounds of the exact solution to any CHprogram. We show that the algorithm is capable of solving many layout optimization problems in deep submicron iterative circuit and/or highperformance multichip module (MCM) and printed circuit board (PCB) designs. In particular, we apply the algorithm to the simultaneous transistor and interconnect sizing problem, and to the global interconnect sizing and spacing problem considering the coupling cap...
Modeling and Optimization of VLSI Interconnects
, 1999
"... As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimizati ..."
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Cited by 6 (0 self)
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As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimization, and interconnect extraction and modeling: the multisource wire sizing (MSWS) problem, the simultaneous transistor and interconnect sizing (STIS) problem, the global interconnect sizing and spacing (GISS) problem, the interconnect capacitance extraction problem, and the interconnect inductance extraction problems. Given a routing tree with multiple sources, the MSWS problem determines the optimal widths of the wire segments such that the delay is minimized. We reveal several interesting properties for the optimal MSWS solution, of which the most important is the bundled refinement property. Based on this property, we propose a polynomial time algorithm, which uses iterative bundled refinement operations to compute lower and upper bounds of an optimal solution. Since the algorithm often achieves identical lower and upper bounds in experiments, the optimal solution is obtained simply by the bound computation. Furthermore, this algorithm can be used for singlesource wire sizing problem and runs 100x xxi faster than previous methods. It has replaced previous singlesource wire sizing methods in practice.