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115
Gate Sizing Using Lagrangian Relaxation Combined with a Fast GradientBased PreProcessing Step
 Proc. ICCAD, 2002
"... Abstract ─ In this paper, we present Forge, an optimal algorithm for gate sizing using the Elmore delay model. The algorithm utilizes Lagrangian relaxation with a fast gradientbased preprocessing step that provides an effective set of initial Lagrange multipliers. Compared to the previous Lagrang ..."
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Cited by 28 (1 self)
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Abstract ─ In this paper, we present Forge, an optimal algorithm for gate sizing using the Elmore delay model. The algorithm utilizes Lagrangian relaxation with a fast gradientbased preprocessing step that provides an effective set of initial Lagrange multipliers. Compared to the previous Lagrangianbased approach, Forge is considerably faster and does not have the inefficiencies due to difficulttodetermine initial conditions and constant factors. We compared the two algorithms on 30 benchmark designs, on a Sun UltraSparc60 workstation. On average Forge is 200 times faster than the previously published algorithm. We then improved Forge by incorporating a slewratebased convex delay model, which handles distinct rise and fall gate delays. We show that Forge is 15 times faster, on average, than the AMPS transistorsizing tool from Synopsys, while achieving the same delay targets and using similar total transistor area. 1
Optimal Wire and Transistor Sizing for Circuits with NonTree Topology
, 1997
"... Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree ..."
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Cited by 26 (8 self)
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Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of significant importance to highperformance deep submicron design including, for example, circuits with loops of resistors, e.g., clock distribution meshes, and circuits with coupling capacitors, e.g., buses with crosstalk between the lines. The paper proposes a new optimization method which can be used to address these problems. The method uses the dominant time constant as a measure of signal propagation delay in an RC circuit, instead of Elmore delay. Using this measure, sizing of any RC circuit can be cast as a convex optimization problem which can be solved using the recently developed efficient interiorpoint methods for semidefinite programming. The method is applied to two important sizing problems sizing of clock meshes, and sizing of buses in the presence of crosstalk.
Transistor Sizing for Minimizing Power Consumption of CMOS Circuits under Delay Constraint
 Proc. of Int'l Symp. on Low Power Design, Monterey CA
, 1995
"... We consider the problem of transistor sizing in a static CMOS layout to minimize the power consumption of the circuit subject to a given delay constraint. Based on our characterization of the short circuit power dissipation of a CMOS circuit we show that the transistors of a gate with high fanout l ..."
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Cited by 21 (0 self)
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We consider the problem of transistor sizing in a static CMOS layout to minimize the power consumption of the circuit subject to a given delay constraint. Based on our characterization of the short circuit power dissipation of a CMOS circuit we show that the transistors of a gate with high fanout load should be enlarged to minimize the power consumption of the circuit. We derive analytical formulation for computing the power optimal size of a transistor and isolate the factor a ecting the power optimal size. We extend our model to analyze powerdelay characteristic of a CMOS circuit and derive the powerdelay optimal size of a transistor. Based on our model we develop heuristics to perform transistor sizing in CMOS layouts for minimizing power consumption while meeting given delay constraints. Experimental results (SPICE simulations) are presented to con rm the correctness of our analytical model. 1
Variability Driven Gate Sizing for Binning Yield Optimization
 IN PROCEEDINGS OF ACM/IEEE DESIGN AUTOMATION CONFERENCE
, 2006
"... Process variations result in a considerable spread in the frequency of the fabricated chips. In high performance applications, those chips that fail to meet the nominal frequency after fabrication are either discarded or sold at a loss which is typically proportional to the degree of timing violatio ..."
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Cited by 19 (0 self)
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Process variations result in a considerable spread in the frequency of the fabricated chips. In high performance applications, those chips that fail to meet the nominal frequency after fabrication are either discarded or sold at a loss which is typically proportional to the degree of timing violation. The latter is called binning. In this paper we present a gate sizingbased algorithm that optimally minimizes the binning yieldloss. We make the following contributions: 1) prove the binning yield function to be convex, 2) do not make any assumptions about the sources of variability, and their distribution model, 3) we integrate our strategy with statistical timing analysis tools (STA), without making any assumptions about how STA is done, 4) if the objective is to optimize the traditional yield (and not binning yield) our approach can still optimize the same to a very large extent. Comparison of our approach with sensitivitybased approaches under fabrication variability shows an improvement of on average 72 % in the binning yieldloss with an area overhead of an average 6%, while achieving a 2.69 times speedup under a stringent timing constraint. Moreover we show that a worstcase deterministic approach fails to generate a solution for certain delay constraints. We also show that optimizing the binning yieldloss minimizes the traditional yieldloss with a 61 % improvement from a sensitivitybased approach.
Interleaving buffer insertion and transistor sizing into a single optimization
 IEEE Transactions on VLSI
, 1998
"... Buffer insertion is a technique that is used either to increase the driving power of a path in a circuit, or to isolate large capacitive loads that lie on noncritical or less critical paths. Gate sizing sets the sizes of gates within a circuit to achieve a given timing specification. Traditional des ..."
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Cited by 17 (0 self)
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Buffer insertion is a technique that is used either to increase the driving power of a path in a circuit, or to isolate large capacitive loads that lie on noncritical or less critical paths. Gate sizing sets the sizes of gates within a circuit to achieve a given timing specification. Traditional design techniques perform gate sizing and buffer insertion as two separate and independent steps during synthesis. However, until sizing is performed, any information on capacitive loads is incomplete and therefore a buffer insertion algorithm must operate with incomplete information, leading to suboptimal results. Moreover, the insertion of buffers can change the structure of the circuit sufficiently so that it may lead to a different sizing solution from the unbuffered circuit. Therefore, these techniques of buffer insertion and sizing are intimately linked and it makes a lot of sense to integrate them into a single optimization. This work presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better powerdelay and areadelay tradeoffs. The purpose of this work is to examine how combining sizing algorithm with buffer insertion will help us achieve better areadelay or powerdelay tradeoffs, and to determine where and when to insert buffers in a circuit. The delay model incorporates placementbased information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results
An Efficient Approach To Simultaneous Transistor And Interconnect Sizing
 IN PROC. INT. CONF. ON COMPUTER AIDED DESIGN
, 1996
"... In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We define a class of optimization problems as CHposynomial programs and reveal a general dominance property for all CHposynomial programs (Theorem 1). We show that the STIS problems under a number of transi ..."
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Cited by 17 (8 self)
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In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We define a class of optimization problems as CHposynomial programs and reveal a general dominance property for all CHposynomial programs (Theorem 1). We show that the STIS problems under a number of transistor delay models are CHposynomial programs and propose an efficient and nearoptimal STIS algorithm based on the dominance property. When used to solve the simultaneous driver/buffer and wire sizing problem for real designs, it reduces the maximum delay by up to 17.7%, and more significantly, reduces the power consumption by a factor of 61.6%, when compared with the original designs. When used to solve the transistor sizing problem, it achieves a smooth areadelay tradeoff. Moreover, the algorithm optimizes a clock net of 367 drivers/buffers and 59304mlong wire in 120 seconds, and a 32bit adder with 1,026 transistors in 66 seconds on a SPARC5 workstation.
A new method for design of robust digital circuits
 Proceedings International Symposium on Quality Electronic Design (ISQED
, 2005
"... As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional circuit optimization methods assuming deterministic gate delays produce a flat “wall ” of equally critical paths, resulting ..."
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Cited by 17 (1 self)
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As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional circuit optimization methods assuming deterministic gate delays produce a flat “wall ” of equally critical paths, resulting in variationsensitive designs. This paper describes a new method for sizing of digital circuits, with uncertain gate delays, to minimize their performance variation leading to a higher parametric yield. The method is based on adding margins on each gate delay to account for variations and using a new “soft maximum ” function to combine path delays at converging nodes. PSfrag Using replacements analytic models to predict the means and standard deterministic deviations method of gate delays as posynomial functions of the device sizes, PDF we create a simple, computationally efficient heuristic for uncertaintyaware sizing of digital circuits via Geometric Programming. MonteCarlo simulations on custom 32bit adders and ISCAS’85 benchmarks show that about 10 % to 20 % delay reduction over deterministic sizing methods can be achieved, without any additional cost in area. 1.
Simultaneous Gate and Interconnect Sizing for CircuitLevel Delay Optimization
 Proceedings of the 32nd Design Automation Conference
, 1995
"... Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuitlevel delay optimization must take interconnect effects into account. Instead of sizing only the gates along the critical paths for delay reduction, the tradeoff possible by simultaneously sizi ..."
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Cited by 16 (1 self)
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Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuitlevel delay optimization must take interconnect effects into account. Instead of sizing only the gates along the critical paths for delay reduction, the tradeoff possible by simultaneously sizing gate and interconnect must also be considered. We show that for optimal gate and interconnect sizing, it is imperative that the interaction between the driver and the RC interconnect load be taken into account. We present an iterative sensitivitybased approach to simultaneous gate and interconnect sizing in terms of a gate delay model which captures this interaction. During each iteration, the path delay sensitivities are efficiently calculated and used to size the components along a path. I.
A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing
 IEEE Transactions on Circuits and SystemsI
, 2004
"... A deterministic activity network (DAN) is a collection of activities, each with some duration, along with a set of precedence constraints, which specify that activities begin only when certain others have finished. One critical performance measure for an activity network is its makespan, which is th ..."
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Cited by 16 (4 self)
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A deterministic activity network (DAN) is a collection of activities, each with some duration, along with a set of precedence constraints, which specify that activities begin only when certain others have finished. One critical performance measure for an activity network is its makespan, which is the minimum time required to complete all activities. In a stochastic activity network (SAN), the durations of the activities and the makespan are random variables. The analysis of SANs is quite involved, but can be carried out numerically by Monte Carlo analysis. This paper concerns the optimization of a SAN, i.e., the choice of some design variables that affect the probability distributions of the activity durations. We concentrate on the problem of minimizing a quantile (e.g., 95%) of the makespan, subject to constraints on the variables. This problem has many applications, ranging from project management to digital integrated circuit (IC) sizing (the latter being our motivation). While there are effective methods for optimizing DANs, the SAN optimization problem is much more difficult; the few existing methods cannot handle largescale problems.
Optimizing dominant time constant in RC circuits
, 1996
"... We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interestin ..."
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Cited by 16 (7 self)
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We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interesting design problems as convex optimization problems, specifically, semidefinite programs (SDPs). For example, assuming that the conductances and capacitances are affine functions of the design parameters (which is a common model in transistor or interconnect wire sizing), one can minimize the power consumption or the area subject to an upper bound on the dominant time constant, or compute the optimal tradeoff surface between power, dominant time constant, and area. We will also note that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires. This approach has two advantages over methods based on Elmore delay optimization. First, it handles a far wider class of circuits, e.g., those with nongrounded capacitors. Second, it always results in convex optimization problems for which very efficient interiorpoint methods have recently been developed. We illustrate the method, and extensions, with several examples involving optimal wire and transistor sizing.