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Modeling and Optimization of VLSI Interconnects
, 1999
"... As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimizati ..."
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As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimization, and interconnect extraction and modeling: the multisource wire sizing (MSWS) problem, the simultaneous transistor and interconnect sizing (STIS) problem, the global interconnect sizing and spacing (GISS) problem, the interconnect capacitance extraction problem, and the interconnect inductance extraction problems. Given a routing tree with multiple sources, the MSWS problem determines the optimal widths of the wire segments such that the delay is minimized. We reveal several interesting properties for the optimal MSWS solution, of which the most important is the bundled refinement property. Based on this property, we propose a polynomial time algorithm, which uses iterative bundled refinement operations to compute lower and upper bounds of an optimal solution. Since the algorithm often achieves identical lower and upper bounds in experiments, the optimal solution is obtained simply by the bound computation. Furthermore, this algorithm can be used for singlesource wire sizing problem and runs 100x xxi faster than previous methods. It has replaced previous singlesource wire sizing methods in practice.
Convex Delay Models for Transistor Sizing
, 2000
"... This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presented and the circuit delay under such a model is shown to be equivalent to a convex function. The richness of these function ..."
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This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presented and the circuit delay under such a model is shown to be equivalent to a convex function. The richness of these functions is exploited to accurately model gate delay for modern designs. The delay model is incorporated into a transistor sizing algorithm based on TILOS. The models were characterized by using a set of grid points and then validated using a disjoint data set. The models were found to be within about 10% of SPICE for nearly all of the gate types considered. Also presented are the experimental results of sizing various test circuits.
Interconnect Design Using Convex Optimization
 Proc. IEEE Custom Integrated Circuits Conf
, 1994
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Mixed Swing Techniques for Low Energy/Operation Datapath Circuits
, 1997
"... The portable communications industry’s vision of integrating a complete multimedia complex on a single die, coupled with the desktop computing industry’s vision of integrating multimedia functionality into generalpurpose microprocessors has transformed lowering the power dissipation of digital si ..."
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The portable communications industry’s vision of integrating a complete multimedia complex on a single die, coupled with the desktop computing industry’s vision of integrating multimedia functionality into generalpurpose microprocessors has transformed lowering the power dissipation of digital signal processing (DSP) datapath circuits into an increasingly important challenge in current and future fabrication processes. Fullystatic CMOS logic accompanied with supply voltage scaling has enjoyed widespread usage in lowering datapath power dissipation over the last decade. However, fundamental limitations preclude device threshold voltage scaling under the constant drainsource field scaling paradigm in future deepsubmicron processes, imposing limitations on voltage scaling. This has motivated a strong necessity for exploring new methodologies to lower the power dissipation of nextgeneration highspeed datapath circuits. This thesis investigates Mixed Swing techniques for reducing the power dissipation of static CMOS datapath operators while retaining their high performance, or
Optimal Design of Macrocells for Low Power and High Speed
, 1996
"... With the emergence of portable products as major players in the electronics market, controlling the power dissipation of integrated circuits is gaining increased importance. While progress is being made in improved battery technology to supply a larger amountofpower per unit weight of the battery, ..."
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With the emergence of portable products as major players in the electronics market, controlling the power dissipation of integrated circuits is gaining increased importance. While progress is being made in improved battery technology to supply a larger amountofpower per unit weight of the battery,itmust also be coupled with an accompanying reduction in the power dissipation of IC's. Even for nonportable applications, as the system complexity increases, it is becoming more and more important to limit the power dissipation so as to avoid additional costs for cooling down electronic systems. In this context, it has become increasingly important to design CMOS digital circuits to ensure a lowpower dissipation. At the same time, however, it is also necessary to ensure that the speed of the circuit is not unduly sacri#ced. An additional consideration is the need for fast system turnaround times, which necessitates the use of semicustom design styles. In this work, we address a
"Conefree" primaldual pathfollowing and potential reduction polynomial time interiorpoint methods
 MATH. PROG
, 2005
"... We present a framework for designing and analyzing primaldual interiorpoint methods for convex optimization. We assume that a selfconcordant barrier for the convex domain of interest and the Legendre transformation of the barrier are both available to us. We directly apply the theory and techni ..."
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We present a framework for designing and analyzing primaldual interiorpoint methods for convex optimization. We assume that a selfconcordant barrier for the convex domain of interest and the Legendre transformation of the barrier are both available to us. We directly apply the theory and techniques of interiorpoint methods to the given good formulation of the problem (as is, without a conic reformulation) using the very usual primal central path concept and a less usual version of a dual path concept. We show that many of the advantages of the primaldual interiorpoint techniques are available to us in this framework and therefore, they are not intrinsically tied to the conic reformulation and the logarithmic homogeneity of the underlying barrier function.
Global injectivity and multiple equilibria in uni and bimolecular reaction networks
, 2012
"... Abstract. Dynamical system models of complex biochemical reaction networks are highdimensional, nonlinear, and contain many unknown parameters. The capacity for multiple equilibria in such systems plays a key role in important biochemical processes. Examples show that there is a very delicate relat ..."
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Abstract. Dynamical system models of complex biochemical reaction networks are highdimensional, nonlinear, and contain many unknown parameters. The capacity for multiple equilibria in such systems plays a key role in important biochemical processes. Examples show that there is a very delicate relationship between the structure of a reaction network and its capacity to give rise to several positive equilibria. In this paper we focus on networks of reactions governed by massaction kinetics. As is almost always the case in practice, we assume that no reaction involves the collision of three or more molecules at the same place and time, which implies that the associated massaction differential equations contain only linear and quadratic terms. We describe a general injectivity criterion for quadratic functions of several variables, and relate this criterion to a network’s capacity for multiple equilibria. In order to take advantage of this criterion we look for explicit general conditions that imply nonvanishing of polynomial functions on the positive orthant. In particular, we investigate in detail the case of polynomials with only one negative monomial, and we fully characterize the case of affinely independent exponents. We describe several examples, including an example that shows how these methods may be used for designing multistable chemical systems in synthetic biology. 1. Introduction. A
A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized
 CMOS and BiCMOS circuits,” in Proc. EURODAC
, 1994
"... This paper presents the first reported discrete gate sizing method to jointly include library optimization capability. The method enables a designer to find the best set of sizes to include in a library and study the tradeoff between the number of gate sizes in a library and circuit peTformance. Co ..."
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This paper presents the first reported discrete gate sizing method to jointly include library optimization capability. The method enables a designer to find the best set of sizes to include in a library and study the tradeoff between the number of gate sizes in a library and circuit peTformance. Compared with continuous sizing, discrete sizing with library optimization, achieves within 270 speed performance using 2X to 5X fewer cells in gbit adders. buffers. This capability is useful when optimizing a BiCMOS technology logic circuit since a BiCMOS gate can typicallly be modeled as a buffered CMOS gate [63. 1
Modeling and Layout Optimization of VLSI Devices and Interconnects in Deep Submicron Design
, 1997
"... This paper presents an overview of recent advances on modeling and layout optimization of devices and interconnects for highperformance VLSI circuit design under the deep submicron technology. First, we review a number of interconnect and driver/gate delay models, which are most useful to guide the ..."
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This paper presents an overview of recent advances on modeling and layout optimization of devices and interconnects for highperformance VLSI circuit design under the deep submicron technology. First, we review a number of interconnect and driver/gate delay models, which are most useful to guide the layout optimization. Then, we summarize the available performance optimization techniques for VLSI device and interconnect layout, including driver and transistor sizing, transistor ordering, interconnecttopology optimization, optimal wire sizing, optimal buffer placement, and simultaneous topology construction, buffer insertion, buffer and wire sizing. The efficiency and impact of these techniques will be discussed in the tutorial.
MacroDriven Circuit Design Methodology for HighPerformance Datapaths
 in Proc. of ACM/IEEE DAC
, 2000
"... Datapath design is one of the most critical elements in the design of a high performance microprocessor. However datapath design is typically done manually, and is often custom style. This adversely impacts the overall productivity of the design team, as well as the quality of the design. In spite o ..."
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Datapath design is one of the most critical elements in the design of a high performance microprocessor. However datapath design is typically done manually, and is often custom style. This adversely impacts the overall productivity of the design team, as well as the quality of the design. In spite of this, very little automation has been available to the designers of high performance datapaths. In this paper we present a new "macrodriven " approach to the design of datapath circuits. Our approach, referred to as SMART (Smart Macro Design Advisor), is based on automatic generation of regular datapath components such as muxes, comparators, adders etc., which we refer to as datapath macros. The generated solution is based on designer provided constraints such as delay, load and slope, and is optimized for a designer provided cost metric such as power, area. Results on datapath circuits of a highperformance microprocessor show that this approach is very effective for both designer productivity as well as design quality.