We present critical-sink routing tree (CSRT) constructions which exploit available critical-path information to yield high-performance routing trees. Our CS-Steiner and "Global Slack Removal" algorithms together modify traditional Steiner tree constructions to optimize signal delay at identified critical sinks. We further propose an iterative Elmore routing tree (ERT) construction which optimizes Elmore delay directly, as opposed to heuristically abstracting linear or Elmore delay as in previous approaches. Extensive timing simulations on industry IC and MCM interconnect parameters show that our methods yield trees that significantly improve (by averages of up to 67%) over minimum Steiner routings in terms of delays to identified critical sinks. ERTs also serve as generic high-performance routing trees when no critical sink is specified: for 8-sink nets in standard IC (MCM) technology, we improve average sink delay by 19% (62%) and maximum sink delay by 22% (52%) over the mini...

We present two critical-sink routing tree (CSRT) constructions which exploit critical-path information that becomes available during timing-driven layout. Our CS-Steiner heuristics with "Global Slack Removal" modify traditional Steiner constructions and produce routing trees with significantly lower criticalsink delays compared with existing performance-driven methods. We also propose a new class of Elmore routing tree (ERT) constructions, which iteratively add tree edges to minimize Elmore delay. This direct optimization of Elmore delay yields trees that improve delays to identified critical sinks by up to 69 % over minimum Steiner routings. ERTs also improve performance over such recent methods as [1] [6] when no critical sinks are specified.

Analysis of Elmore delay in distributed RC tree structures shows the influence of both tree cost and tree radius on signal delay in VLSI interconnects. We give new and efficient interconnection tree constructions that smoothly combine the minimum cost and the minimum radius objectives, by combining respectively optimal algorithms due to Prim and Dijkstra. Previous "shallow-light" techniques [2, 3, 8, 13] are both less direct and less effective: in practice, our methods achieve uniformly superior cost-radius tradeoffs. Detailed timing simulations for a range of IC and MCM interconnect technologies show that our wirelength savings yield reduced signal delays when compared to shallow-light or standard minimum spanning tree and Steiner tree routing. 1 Introduction and Motivation With the scaling of device technology and die size, interconnection delay now contributes up to 50% to 70% of the clock cycle in dense, high performance circuits [4]. Performance-driven layout design has therefore ...

Motivated by analysis of distributed RC delay in routing trees, we propose a new tree construction for performance-driven global routing which directly trades off between Prim's minimum spanning tree algorithm and Dijkstra's shortest path tree algorithm. This direct combination of two objective functions and their corresponding optimal algorithms contrasts with the more indirect "shallow-light" methods of [2, 4, 10]. Our method achieves routing trees which satisfy a given routing tree radius bound while using less wire than previous methods. Detailed simulations show that this wirelength savings translates into significantly improved delay over both the method of [4] and standard MST routing in both IC and multi-chip module (MCM) interconnect technologies.

Abstract. The limiting factor for high-performance systems is being set by interconnection delay rather than tran-sistor switching speed. The advances in circuits speed and density are placing increasing demands on the perform-ance of interconnections, for example chip-to-chip interconnection on multichip modules. To address this extreme-ly important and timely research area, we analyze in this paper the circuit property of a generic distributed RLC tree which models interconnections in high-speed IC chips. The presented result can be used to calculate the waveform and delay in an RLC tree. The result on the RLC tree is then extended to the case of a tree consisting of transmis-sion lines. Based on an analytical approach a two-pole circuit approximation is presented to provide a closed form solution. The approximation reveals the relationship between circuit performance and the design parameters which is essential to IC layout designs. A simplified formula is derived to evaluate the performance of VLSI layout. 1.

Existing routing problems for delay minimization consider the connection of a single source node to a number of sink nodes, with the objective of minimizing the delay from the source to all sinks, or a set of critical sinks. In this paper, we study the problem of routing nets with multiple sources, such as those found in signal busses. This new model assumes that each node in a net may be a source, a sink, or both. The objective is to optimize the routing topology to minimize the total weighted delay between all node pairs (or a subset of critical node pairs). We present a heuristic algorithm for the multiple-source performance-driven routing tree problem based on efficient construction of minimum-diameter minimum-cost Steiner trees. Experimental results on random nets with submicron CMOS IC and MCM technologies show an average of 12.6% and 21% reduction in the maximum interconnect delay, when compared with conventional minimum Steiner tree based topologies. Experimental results on mul...

Existing routing problems for delay minimization consider the connection of a single source node to a number of sink nodes, with the objective of minimizing the delay from the source to all sinks, or a set of critical sinks. In this paper, we study the problem of routing nets with multiple sources, such as those found in signal busses. This new model assumes that each node in a net may be a source, a sink, or both. The objective is to optimize the routing topology to minimize the total weighted delay between all node pairs (or a subset of critical node pairs). We present a heuristic algorithm for the multiple-source performancedriven routing tree problem based on efficient construction of minimumdiameter minimum-cost Steiner trees. Experimental results on random nets with submicrometer CMOS IC and MCM technologies show an average of 12.6% and 21% reduction in the maximum interconnect delay, when compared with conventional minimum Steiner tree based topologies. Experimental results on multisource nets extracted from an Intel processor show as much as a 16.1% reduction in the maximum interconnect delay, when compared with conventional minimum Steiner tree based topologies.

As the clock frequencies used in industrial applications increase, the timing requirements on routing problems become tighter, and current routing tools can not successfully handle these constraints anymore. In this paper, we focus on the high-performance singlelayer bus routing problem, where the objective is to match the lengths of all nets belonging to each bus. An effective approach to solve this problem is to allocate extra routing resources around short nets during routing; and use those resources for length extension afterwards. We first propose a provably optimal algorithm for routing nets with min-area max-length constraints. Then, we extend this algorithm to the case where minimum constraints are given as exact length bounds. We also prove that this algorithm is optimal within a constant factor. Both algorithms proposed are also shown to be scalable for large circuits, since the respective time complexities are O(A) and O(AlogA), where A is the area of the intermediate region between chips. 1.

As die sizes are shrinking, and circuit complexities are increasing, the PCB routing problem becomes more and more challenging. Traditional routing algorithms can not handle these challenges effectively, and many high end designs in the industry require manual routing efforts. In this paper, we propose novel routing algorithms that can handle these new challenges effectively. The first algorithm we propose is a Lagrangian relaxation based length matching algorithm for routing high-speed bus structures. Then, we focus on a more restricted yet common problem: routing highspeed bus structures between two components across a channel. For this problem, we propose an algorithm to route nets on x-y layer pairs. However, for some board designs, buried vias are forbidden due to high manufacturing costs. For these types of designs, we propose a routing algorithm that can route nets within tight minimum and maximum length bounds on a single layer. After that, we propose an escape routing and layer assignment algorithm that finds the routing solution within multiple components simultaneously. 1.