Abstract. The two dimensional fast Fourier transform (2-D FFT) is an indispensable operation in many digital signal processing applications but yet is deemed computationally expensive when performed on a conventional general purpose processors. This paper presents the implementation and performance figures for the Fourier transform on a FPGA-based custom computer. The computation of a 2-D FFT requires O(N2 log2N) floating point arithmetic operations for an NxN image. By implementing the FFT algorithm on a custom computing machine (CCM) called Splash-2, a computation speed of 180 Mflops and a speed-up of 23 times over a Sparc-10

A new optimization to reduce the overhead of rollback in optimistically synchronized simulation is proposed. This optimization is called rollback relaxation and it eliminates the need to rollback processes that satisfy certain constraints. A process qualies for rollback relaxation if its output is completely determined by its input(s) at all times. That is, if the process has single entry/exit points and if no internal variables are live upon entry into the process. Rollback relaxation is an optimization that saves both time and space. An initial examination of processes in a collection of digital system descriptions has shown that an average of 74% of all processes qualify for rollback relaxation. Furthermore, in hand crafted simulations, four descriptions presented a performance improvement of between 12 and 46 percent when rollback relaxation was employed. Key Words: Time Warp, Optimistic Synchronization, Digital Systems 1 Introduction Parallel discrete event driven simulators tha...

Asynchronous Transfer Mode (ATM) is one of the keywords in modern telecommunication. It is believed to become the most common and widespread network in the near future due to its unique capability to effectively ally different types of information like e.g. data, voice and video in one transmission path. Due to the increasing demand for high bandwidth information delivery to the homes, many efforts have been made to standardise ATM networks and to develop appropriate hardware equipment such as multiplexers and network terminals. The progress in the MOS integration technology has reached deep sub-micron levels and provides the capability of including a virtually unlimited amount of functionality in those network components. To keep track with that trend and to ensure the detection of errors early in the design cycle, the use of high level specification languages, such as SDL, has been well established in the area of software design. Recent research, however, has shown the applicability ...

syntax for design annotations : : : : : : : : : : : : : : : : : 45 4.3 Semantic algebras for design annotations : : : : : : : : : : : : : : : : 46 4.4 Semantic algebras, continued : : : : : : : : : : : : : : : : : : : : : : : 47 4.5 Valuation functions for design annotations : : : : : : : : : : : : : : : 48 4.6 Devices : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 50 5.1 Constant dummy in the basic library : : : : : : : : : : : : : : : : : : 58 5.2 Interconnection devices in the basic library : : : : : : : : : : : : : : : 58 5.3 Devices in the comp library : : : : : : : : : : : : : : : : : : : : : : : 59 5.4 Timing analysis of the design in session box 7 : : : : : : : : : : : : : 66 5.5 Scheduling the design in session box 7 : : : : : : : : : : : : : : : : : : 67 5.6 The design after session box 8 : : : : : : : : : : : : : : : : : : : : : : 68 5.7 The design after session box 15 : : : : : : : : : : : : : : : : : : : : : 74 5.8 The design after session box 16 : : :...

We present in this paper a novel control synthesis technique for system-level specifications that are better described as a set of concurrent synchronous descriptions, their synchronizations and constraints'. The proposed synthesis ' technique considers' the degrees of freedom introduced by the concurrent models' and by the environment in order to satisfy the design constraints'.

The hardware description language TDL has been designed with the goal to generate machine-dependent postpass optimizers and analyzers from a concise specification of the target processor. TDL is assembly-oriented and provides a generic modeling of irregular hardware constraints that are typical for many embedded processors. The generic modeling supports graph-based and search-based optimization algorithms. An important design goal of Tdl was to achieve extendibility, so that TDL can be easily integrated in different target applications. TDL is at the base

This thesis presents a new application of analyzing Asynchronous Communication Mechanisms (ACMs) using Petri nets. This technique facilitates the testing of essential ACM operating properties: data coherence (concurrent reading and writing of data at the same location should not happen), data freshness (not reading out of date data) and data sequencing (not reading data in a new-old-new order). The technique allows for analysis under metastable conditions which cannot be avoided in an asynchronous environment, but have usually been omitted in the analysis of published ACM algorithms. The modelling techniques are described, along with the analysis methods and optimizations which allow the ACM models to be as compact as possible without omitting necessary detail. The method allows for fast automated analysis of ACMs therefore allowing design changes in the algorithms to be quickly analyzed, without the need to perform long formal proofs. The use of a common analysis method allows compari...

In order to design advanced processors in a short time, designers must simulate their designs and reflect the results to the designs at the very early stages. However, conventional hardware description languages (HDLs) do not have enough ability to describe designs easily and accurately at these stages. Then, we have proposed a new hardware description language AIDL. In this paper, in order to evaluate the effectiveness of AIDL, we describe and compare three processors in AIDL and VHDL descriptions.

ion and Symbolic Model Checking ? Tom Bienmuller 1 , Udo Brockmeyer 2 , Werner Damm 2 , Gert Dohmen 2 , Claus Eßmann 2 , Hans-Jurgen Holberg 2 , Hardi Hungar 2 , Bernhard Josko 2 , Rainer Schlor 2 , Gunnar Wittich 2 , Hartmut Wittke 2 , Geoffrey Clements 3 , John Rowlands 3 , and Eric Sefton 3 1 Carl von Ossietzky Universitat Oldenburg, Germany 2 OFFIS, Escherweg 2, 26121 Oldenburg, Germany 3 British Aerospace, Warton Aerodrome, Preston, PR4 1AX Lancashire, UK Abstract. This paper demonstrates the use of model-checking based verification technology to establish safety critical properties for an industrial avionics application. The verification technology is tightly integrated with the Statemate r fl system of i-Logix Inc., USA. Key features of this technology are its scalalability to complete system verification, the powerful debugging capabilities, graphical entry for safety critical properties, and the capability to re-use verification results for d...

this paper, we formally specify and verify the correctness of rollback relaxation. The problem is specified using the PVS Specification Language and proved using the PVS Prover. 1 Introduction Discrete event simulation is a key tool for system design and analysis. As systems grow in complexity, the need for higher throughput of discrete event simulators has increased. This has led to the development of techniques for parallel simulation and to the emergence of distributed synchronization algorithms for parallel simulation [4, 13]. Two approaches to distributed synchronization exist: conservative [13,18], and optimistic [2, 9]. In conservative approaches, the