There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and delay of the resulting system. Crossbar, Hierarchical Crossbar, and Mesh interconnection schemes have all been proposed for use in FPGA-based systems. In this paper we examine Mesh interconnection schemes, and propose several constructs for more efficient topologies. These reduce inter-chip delays by more than 60% over the basic 4-way Mesh.

This paper describes a novel hardware accelerator for Monte Carlo (MC) simulation, and illustrates its implementation in field programmable gate array (FPGA) technology for speeding up financial applications. Our accelerator is based on a generic architecture, which combines speed and flexibility by integrating a pipelined MC core with an on-chip instruction processor. We develop a generic number system representation for determining the choice of number representation that meets numerical precision requirements. Our approach is then used in a complex financial engineering application, involving the Brace, G¸atarek and Musiela (BGM) interest rate model for pricing derivatives. We address, in our BGM model, several challenges including the generation of Gaussian distributed random numbers and pipelining of the MC simulation. Our BGM application, based on an off-the-shelf system with a Xilinx XC2VP30 device at 50 MHz, is over 25 times faster than software running on a 1.5 GHz Intel Pentium machine. 1

FPGA systems outperform many ASIC and super computer systems through effective use of the reconfigurable resource. Reusing design effort across different applications requires a standard, flexible software environment. Driving FPGA systems from ANSI C is possible using lcc (an ANSI C compiler) targeted at an FPGA system and dasm (a retargetable, flexible assembler) . The compiler supports custom hardware capabilities of FPGA systems, as well as all constructs of C. The assembler reads instruction definitions at assemble time, allowing the user to add new custom hardware functions which dasm can assemble correctly to an instruction stream the hardware executes. A source code debugger has been implemented for this system. 1 Introduction FPGAs are capable of achieving high performance on many application-specific tasks. In many cases performance achievable with FPGAs on certain applications exceeds comparable ASIC designs or even super computers[2, 7]. One approach used in obtaining this...

As computing platforms gain greater and greater computational power, new applications that previously were unthinkable are being developed. One such application is the ability to automatically identify objects in radar images called Automatic Target Recognition (ATR). This thesis specifically deals with ATR algorithms developed to search for objects in Synthetic Aperture Radar (SAR) images. The algorithms require more computational power than is currently available in any platforms. These algorithms were used as a tool to compare two reconfigurable hardware platforms because of these high computational requirements. Two implementations of ATR for SAR have been developed to compare Teramac and Splash-2 Field Programmable Gate Array (FPGA) based platforms. This comparison shows Teramac's strength as an exploratory platform and Splash-2's strength as an implementation platform for linear systolic array designs. COMMITTEE APPROVAL: Brad L. Hutchings, Committee Chairman James K. Archibald, ...

We are currently exploring the use of reconfigurable computing using Field Programmable Gate Arrays (FPGAs) to accelerate kernels of scientific applications. Here, we present a hardware architecture targeted towards the acceleration of two scientific kernels in a Quantum Monte Carlo (QMC) application applied to N-body systems. Quantum Monte Carlo methods enable us to determine the ground-state properties of atomic or molecular clusters. Here, we focus on two key kernels of the QMC application: acceleration of potential energy and wavefunction calculations. Our current platform consisting of a dual processor Intel Xeon 2.4 GHz augmented with two reconfigurable FPGA development boards provides a 3x speedup over the equivalent software only implementation. Targeting our design onto a High Performance Computing (HPC) system like the Cray XD1 or XT4 platform with high gate-density FPGAs will allow us to operate multiple instances of our design thereby providing additional parallelism. 1.

this document. An excellent treatment can be found in [7]. In brief, however, Reed-Solomon codes arrived on the scene in 1960 and are named for their developers, Reed and Solomon. These codes allow the receiver to correct burst errors that may occur during transmission. They do so by appending carefully-crafted, redundant information to a block of data where the additional information serves to check the correctness of the transmission at the receiver