Abstract. Design automation for embedded systems comprising both hardware and software components demands for code generators integrated into electronic CAD systems. These code generators provide the necessary link between software synthesis tools in HW/SW codesign systems and embedded processors. General-purpose compilers for standard processors are often insu cient, because they do not provide exibility with respect to di erent target processors and also su er from inferior code quality. While recent research on code generation for embedded processors has primarily focussed on code quality issues, in this contribution we emphasize the importance of retargetability, and we describe an approachtoachieve retargetability. We propose usage of uniform, external target processor models in code generation, which describe embedded processors by means of RT-level netlists. Such structural models incorporate more hardware details than purely behavioral models, thereby permitting a close link to hardware design tools and fast adaptation to di erent target processors. The MSSQ compiler, which is part of the MIMOLA hardware design system, operates on structural models. We describe input formats, central data structures, and code generation techniques in MSSQ. The compiler has been successfully retargeted to a number of real-life processors, which proves feasibility of our approach with respect to retargetability. We discuss capabilities and limitations of MSSQ, and identify possible areas of improvement.

DSP algorithms in most cases are subject to hard real-time constraints. In case of programmable DSP processors, meeting those constraints must be ensured by appropriate code generation techniques. For processors offering instruction-level parallelism, the task of code generation includes code compaction. The exact timing behavior of a DSP program is only known after compaction. Therefore, real-time constraints should be taken into account during the compaction phase. While most known DSP code generators rely on rigid heuristics for that phase, this paper proposes a novel approach to local code compaction based on an Integer Programming model, which obeys exact timing constraints. Due to a general problem formulation, the model also obeys encoding restrictions and possible side effects. 1 1 Introduction & related work Design requirements for embedded systems including DSP functionality strongly differ from those for interactive environments such as workstations. While in the latter ca...

Besides high code quality, a primary issue in embedded code generation is retargetability of code generators. This paper presents techniques for automatic generation of code selectors from externally specified processor models. In contrast to previous work, our retargetable compiler Record does not require tool-specific modelling formalisms, but starts from general HDL processor models. From an HDL model, all processor aspects needed for code generation are automatically derived. As demonstrated by experimental results, short turnaround times for retargeting are achieved, which permits to study the HW/SW trade-off between processor architectures and program execution speed.

In this paper we present a uni ed frontend for retargetable compilers that performs analysis of the target processor model. Our approach bridges the gap between structural and behavioral processor models for retargetable compilation. This is achieved by means of instruction set extraction. The extraction technique is based on a BDD data structure which signi cantly improves control signal analysis in the target processor compared to previous approaches. 1 1

This paper describes how a modular machine description, which specifies the functionality and the binary representation of an instruction set, can be transformed into a hardware model. This model is built from few generic hardware entities (registers, memories, arithmetic/logic operators, selectors and connections) and may eventually serve as an input to high-level hardware synthesis tools. The transformation steps on the way from the machine description to the hardware model are explained by giving an example.

When developing software for embedded systems, the set of essential tools includes a compiler and an instruction set simulator. Since software and hardware are often designed in parallel, the tools must be easily adaptable to the changing target architecture. For the compiler, its back-end (the code generator) must be retargetable. Abstraction from the target machine is the key to an automated approach. Additionally, abstraction from tool-internal strategies permits the utilization of a unified machine description for all tools. In this chapter, the machine description formalism nML is presented along with the retargetable code generator Cbc and the instruction set simulation environment Sigh/Sim. 1 INTRODUCTION For the realization of retargetable software development tools such as a code generator and an instruction set simulator, several aspects of the potential target machines must be modeled in an abstract manner. These machine models are necessary to formalize the tool's methods...

. We describe a novel technique for code selection based on data-flow graphs, which arise naturally in the domain of digital signal processing. Code selection is the optimized mapping of abstract operations to partial machine instructions. The presented method performs an important task within the retargetable microcode generator CBC, which was designed to cope with the requirements arising in the context of custom digital signal processor (DSP) programming. The algorithm exploits a graph representation in which control-flow is modeled by scopes. 1 Introduction In the domain of medium-throughput digital signal processing, micro-programmable processor cores are frequently chosen for system realization. By adding dedicated hardware (accelerator paths), these cores are tailored to the needs of new applications. Optimized processor modules can be reused, which is a major benefit compared to high-level synthesis [28] where a completely new design is developed for each application. ...

The concept of retargetability enables compiler technology to keep pace with the increasing variety of domain-specific embedded processors. In order to achieve user retargetability, powerful processor modeling formalisms are required. Most of the recent modeling formalisms concentrate on horizontal, VLIWlike instruction formats. However, for encoded instruction formats with restricted instruction-level parallelism (ILP), a large number of ILP constraints might need to be specified, resulting in less concise processor models. This paper presents an HDL-based approach to processor modeling for retargetable compilation, in which ILP may be implicitly constrained. As a consequence, the formalism allows for concise models also for encoded instruction formats. The practical applicability of the modeling formalism is demonstrated by means of a case study for a complex DSP 1 1 Introduction As a result of the increasing diversity of embedded processors, retargetable compilers have received re...

... this article novel approximation techniques for ILP-based code optimization are presented. The presented approximation techniques mostly produce optimal results while reducing the computation time by orders of magnitude compared to the exact solution. The PROPAN framework has been retargeted to several representative standard digital signal processors. Practical experiments demonstrate the applicability of this approach.

The demand for decreased turn around time in the design of programmable digital circuits requires CAD tools for synthesis, verification and code generation. Usually a RT level netlist is available as soon as the datapath is designed. Given the netlist and the behavior of the RT level modules, the proposed compiler maps a source program to the binary code of the target machine. The main tasks of the compiler are allocation, register allocation, scheduling and compaction. These tasks are highly interdependent. Some machine features such as operator chaining, multi-cycle operations, pipeline latency, load delay, delayed branch, or residual control give raise to instruction dependencies, which can be automatically extracted from the structural description. From the netlist the proposed compiler derives an internal target machine representation, that is general enough to support all target architecture features mentioned above. In case the hardware supports different operators for a given o...