We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [BRV 89]. Based on Programmable Gate Array (PGA) technology, the PAM is a universal hardware co-processor closely coupled to a standard host computer. The PAM can speed up many critical software applications running on the host, by executing part of the computations through a specific hardware PAM design. The performance measurements presented are based on two PAM architectures and ten specific applications, drawn from arithmetics, algebra, geometry, physics, biology, audio and video. Each of these PAM designs proves as fast as any reported hardware or super-computer for the corresponding application. In cases where we could bring some genuine algorithmic innovation into the design process, the PAM has proved an order of magnitude faster than any previously existing system (see [SBV 91] and [S 92]). 1 PAM concept Like any RAM memory module, a PAM is att...

The future Large Hadron Collider (LHC) to be built at CERN 1 , by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST 2 (RD-11) group and DECPRL PAM 3 team. We present the implementations of the three foremost LHC algorithms on DECPeRLe-1 [2]. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based board built for just one of the algorithm [3]. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both. 1 Introduction 1.1 High-Energy Physics The community of High-Energy Physics is about to decide to go forward with the next generation collider to be built at CERN, the LHC. With this new instrument, it will be possible to observe proton-proton collisions of 8000 GeV, an energy not at...

We present the design and performance of a non-adaptive hardware system for data compression by arithmetic coding. The alphabet of the data source is the full 256-symbol ASCII character set, plus a non-ASCII end-of-file symbol. The key ideas of our system are ffl the non-arithmetic representation of the current interval width, which yields improved coding efficiency in the interval-width update, and ffl a retimed circuit for the code point update, which removes this step from the critical path of the system's operation. Through a further retiming, the lower bound on this circuit's clock period can be reduced to a constant, independent of its width in bits. We have implemented and tested the system on a reconfigurable coprocessor, which is constructed from commercially available field-programmable gate arrays and static RAM. This implementation compresses its input stream at better than 16 MBytes/sec. 1 Introduction Arithmetic coding is a well-known method for lossless data compressi...

We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [BRV89]. Based on Field Programmable Gate Array (FPGA) technology, the PAM is a universal hardware co-processor closely coupled to a standard host computer. The PAM can speed up many critical software applications running on the host, by executing part of the computations through a specific hardware design. The performance measurements presented are based on two PAM architectures and ten specific applications, drawn from arithmetics, algebra, geometry, physics, biology, audio and video. Each of these PAM designs proves as fast as any reported hardware or super-computer for the corresponding application. In cases where we could bring some genuine algorithmic innovation into the design process, the PAM was measured to be an order of magnitude faster than any previously existing system (see [SBV91] and [Sku92]). 1 PAM concept Like any RAM memory module, a...

We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [BRV89]. Based on Field Programmable Gate Array (FPGA) technology, the PAM is a universal hardware co-processor closely coupled to a standard host computer. The PAM can speed up many critical software applications running on the host, by executing part of the computations through a specific hardware design. The performance measurements presented are based on two PAM architectures and ten specific applications, drawn from arithmetics, algebra, geometry, physics, biology, audio and video. Each of these PAM designs proves as fast as any reported hardware or super-computer for the corresponding application. In cases where we could bring some genuine algorithmic innovation into the design process, the PAM was measured to be an order of magnitude faster than any previously existing system (see [SBV91] and [Sku92]). R esum e Nous presentons quelques mesures qua...