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33
Statistical timing analysis considering spatial correlations using a single PERTlike traversal
 In ICCAD
"... We present an efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay while incorporating the effects of spatial correlations of intradie parameter variations, using a method based on principal component analysis. The method uses a PERTlike c ..."
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Cited by 169 (15 self)
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We present an efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay while incorporating the effects of spatial correlations of intradie parameter variations, using a method based on principal component analysis. The method uses a PERTlike circuit graph traversal, and has a runtime that is linear in the number of gates and interconnects, as well as the number of grid partitions used to model spatial correlations. On average, the mean and standard deviation values computed by our method have errors of and, respectively, in comparison with a Monte Carlo simulation. delays), as explained in Section 2. Moreover, any strictly pathbased method will eventually be faced with an explosion in the number of critical paths. We propose an algorithm for statistical STA that computes the distribution of circuit delay while considering correlations due to path reconvergence as well as spatial correlations. We model the circuit delay as a correlated multivariate normal distribution, considering both gate and wire delay variations. The complexity of the algorithm is, which is linear in the number of gates and interconnects, and also linear in the number of grids that are used to model the variational regions. In other words, the cost is, at worst, times the cost of a deterministic STA. 1.
BlockBased static timing analysis with uncertainty
 In Proceedings of the IEEE/ACM International Conference on ComputerAided Design
, 2003
"... Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process variations which need to be incorporated in static timing analysis. This paper presents a new, efficient and accurate bloc ..."
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Cited by 74 (0 self)
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Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process variations which need to be incorporated in static timing analysis. This paper presents a new, efficient and accurate blockbased static timing analysis technique considering uncertainty. This new method is more efficient as its models arrival times as cumulative density functions (CDFs) and delays as probability functions (PDFs). Computationally simple expression are presented for basic static timing operations. The techniques are valid for any form of the probability distribution, though the use piecewise linear modeling of CDFs is highlighted in this paper. Reconvergent fanouts are handled using a new technique that avoids path tracing. Variable accuracy timing analysis can be performed by varying the modeling accuracy of the piecewise linear model. Regular and statistical timing on different parts of the circuit can be incorporated into a single timing analysis run. Accuracy and efficiency of the proposed method is demonstrated for various ISCAS benchmark circuits. 1.
Death, Taxes and Failing Chips
, 2003
"... In the way they cope with variability, presentday methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important aspect of highperformance digital integrated circuit design, and indispensable for firsttimeright hardware and cuttinged ..."
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Cited by 50 (3 self)
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In the way they cope with variability, presentday methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important aspect of highperformance digital integrated circuit design, and indispensable for firsttimeright hardware and cuttingedge performance. This invited paper discusses the methodology, analysis, synthesis and modeling aspects of this problem. These aspects of the problem are compared and contrasted in the ASIC and custom (microprocessor) domains. This paper pays particular attention to statistical timing analysis and enumerates desirable attributes that would render such an analysis capability practical and accurate.
A General Framework for Accurate Statistical Timing Analysis Considering Correlations
 In DAC
, 2005
"... The impact of parameter variations on timing due to process and environmental variations has become significant in recent years. With each new technology node this variability is becoming more prominent. In this work, we present a general Statistical Timing Analysis (STA) framework that captures spa ..."
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Cited by 27 (6 self)
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The impact of parameter variations on timing due to process and environmental variations has become significant in recent years. With each new technology node this variability is becoming more prominent. In this work, we present a general Statistical Timing Analysis (STA) framework that captures spatial correlations between gate delays. Our technique does not make any assumption about the distributions of the parameter variations, gate delay and arrival times. We propose a Taylorseries expansion based polynomial representation of gate delays and arrival times which is able to e#ectively capture the nonlinear dependencies that arise due to increasing parameter variations. In order to reduce the computational complexity introduced due to polynomial modeling during STA, we propose an e#cient linearmodeling driven polynomial STA scheme. On an average the degree2 polynomial scheme had a 7.3x speedup as compared to Monte Carlo with 0.049 units of rms error w.r.t Monte Carlo. Our technique is generic and can be applied to arbitrary variations in the underlying parameters.
Digital Circuit Optimization via Geometric Programming
 Operations Research
, 2005
"... informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently s ..."
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Cited by 27 (7 self)
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informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistorcapacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.
Gate Sizing Using Incremental Parameterized Statistical Timing Analysis
 In ICCAD
, 2005
"... Abstract — As technology scales into the sub90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as statistical distributions during both analysis and optimization. This paper uses incremental, parametric statistical ..."
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Cited by 25 (1 self)
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Abstract — As technology scales into the sub90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as statistical distributions during both analysis and optimization. This paper uses incremental, parametric statistical static timing analysis (SSTA) to perform gate sizing with a required yield target. Both correlated and uncorrelated process parameters are considered by using a firstorder linear delay model with fitted process sensitivities. The fitted sensitivities are verified to be accurate with circuit simulations. Statistical information in the form of criticality probabilities are used to actively guide the optimization process which reduces runtime and improves area and performance. The gate sizing results show a significant improvement in worst slack at 99.86 % yield over deterministic optimization. I.
CorrelationPreserved NonGaussian Statistical Timing Analysis With Quadratic Timing Model
, 2005
"... Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing and operational variations become more and more significant. Due to the nonlinearity of the mapping from variation sources ..."
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Cited by 25 (1 self)
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Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing and operational variations become more and more significant. Due to the nonlinearity of the mapping from variation sources to the gate/wire delay, the distribution of the delay is no longer Gaussian even if the variation sources are normally distributed. Anovelquadratic timing model is proposed to capture the nonlinearity of the dependency of gate/wire delays and arrival times on the variation sources. Systematic methodology is also developed to evaluate the correlation and distribution of the quadratic timing model. Based on these, a novel statistical timing analysis algorithm is propose which retains the complete correlation information during timing analysis and has the same computation complexity as the algorithm based on the canonical timing model. Tested on the ISCAS circuits, the proposed algorithm shows 10 × accuracy improvement over the existing first order algorithm while no significant extra runtime is needed.
Manufacturingaware physical design
 In Proc. of the International Conference on Computer Aided Design (ICCAD
, 2003
"... Ultradeep submicron manufacturability impacts physical design (PD) through complex layout rules and large guardbands for process variability; this creates new requirements for new manufacturingaware PD technologies. The first part of this tutorial reviews PD complications and methodology changes ..."
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Cited by 23 (6 self)
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Ultradeep submicron manufacturability impacts physical design (PD) through complex layout rules and large guardbands for process variability; this creates new requirements for new manufacturingaware PD technologies. The first part of this tutorial reviews PD complications and methodology changes notably in the detailed routing arena that arise from subwavelength lithography and deepsubmicron manufacturing (antennas, metal planarization and maskwafer mismatch). Process variations and their sources are taxonomized for modeling and simulation. A framework of design for cost and value is described. The second part covers yieldconstrained optimizations in PD, especially “beyond corners ” approaches that escape today’s pessimistic or even incorrect cornerbased approaches. Statistical timing and noise analyses enable optimization of parametric yield and reliability. Yieldaware cell libraries and “analog ” design rules (as opposed to “digital”, 0/1 rules) can help designers explore yieldcost tradeoffs, especially for lowvolume parts. We then examine performance impactlimited fill insertion which goes beyond mere capacitance rules. Modeling, objectives, and filling strategies are discussed. Finally, we discuss current and nearterm prospects for the overall designtomanufacturing PD methodology. Key aspects include better integrations with analysis and manufacturing interfaces, as well as costbenefit tradeoffs for “regular” layout structures that are likely beyond 90nm, cost optimizations for lowvolume production, and the role of robust and/or stochastic optimization in PD. 1
Defining statistical sensitivity for timing optimization of logic circuits with largescale process and environmental variations,” Docket MC06172004P, Filed with the US Patent Office
, 2005
"... The largescale process and environmental variations for today’s nanoscale ICs are requiring statistical approaches for timing analysis and optimization. Significant research has been recently focused on developing new statistical timing analysis algorithms, but often without consideration for how o ..."
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Cited by 20 (3 self)
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The largescale process and environmental variations for today’s nanoscale ICs are requiring statistical approaches for timing analysis and optimization. Significant research has been recently focused on developing new statistical timing analysis algorithms, but often without consideration for how one should interpret the statistical timing results for optimization. In this paper [1] we demonstrate why the traditional concepts of slack and critical path become ineffective under largescale variations, and we propose a novel sensitivitybased metric to assess the “criticality ” of each path and/or arc in the statistical timing graph. We define the statistical sensitivities for both paths and arcs, and theoretically prove that our path sensitivity is equivalent to the probability that a path is critical, and our arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples. 1.
A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing
 IEEE Transactions on Circuits and SystemsI
, 2004
"... A deterministic activity network (DAN) is a collection of activities, each with some duration, along with a set of precedence constraints, which specify that activities begin only when certain others have finished. One critical performance measure for an activity network is its makespan, which is th ..."
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Cited by 12 (4 self)
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A deterministic activity network (DAN) is a collection of activities, each with some duration, along with a set of precedence constraints, which specify that activities begin only when certain others have finished. One critical performance measure for an activity network is its makespan, which is the minimum time required to complete all activities. In a stochastic activity network (SAN), the durations of the activities and the makespan are random variables. The analysis of SANs is quite involved, but can be carried out numerically by Monte Carlo analysis. This paper concerns the optimization of a SAN, i.e., the choice of some design variables that affect the probability distributions of the activity durations. We concentrate on the problem of minimizing a quantile (e.g., 95%) of the makespan, subject to constraints on the variables. This problem has many applications, ranging from project management to digital integrated circuit (IC) sizing (the latter being our motivation). While there are effective methods for optimizing DANs, the SAN optimization problem is much more difficult; the few existing methods cannot handle largescale problems.