A parallel prefix circuit takes n inputs x1 , x2 , . . . , xn and produces the n outputs x1 , x1 x2 , . . . , x1 x2 xn , where `#' is an arbitrary associative binary operation. Parallel prefix circuits and their counterparts in software, parallel prefix computations or scans, have numerous applications ranging from fast integer addition over parallel sorting to convex hull problems. A parallel prefix circuit can be implemented in a variety of ways taking into account constraints on size, depth, or fanout. Traditionally, implementations are either defined graphically or by enumerating the underlying graph. Both approaches have their pros and cons. A figure if well drawn conveys the possibly recursive structure of the scan but it is not amenable to formal manipulation. A description in form of a graph while rigorous obscures the structure of a scan and is equally hard to manipulate. In this paper we show that parallel prefix circuits enjoy a very pleasant algebra. Using only two basic building blocks and four combinators all standard designs can be described succinctly and rigorously. The rules of the algebra allow us to prove the circuits correct and to derive circuit designs in a systematic manner. lord darlington. . . . [Sees a fan lying on the table.] And what a wonderful fan! May I look at it? lady windermere. Do. Pretty, isn't it! It's got my name on it, and everything. I have only just seen it myself. It's my husband's birthday present to me. You know to-day is my birthday? --- Oscar Wilde, Lady Windermere's Fan 1

Commercial fine-grained FPGA architectures are known to be 50 times slower than custom circuits for structured logic such as ALUs and multipliers [Ebeling1996]. Many architectures have tried to incorporate coarse-grained structures on reconfigurable platforms to speed up arithmetic operations, because generally speed and area improve with increasing granularity for these operations. This thesis proposes a novel building block for arithmetic structures for reconfigurable computing. The building block is capable of performing many arithmetic operations including addition/subtraction of 16 or 32-bit operands, multiplication of 8-bit operands, comparison and logical operations such as AND, OR, Exclusive-OR operations on 16-bit operands. Multiple blocks can be used together to perform these computations on larger word-sizes. Synthesis results show that the area of the reconfigurable arithmetic block is 17,579 square microns in a 0.11 micron standard cell technology. The delay for 8x8-bit multiplication is 2.48ns and 32-bit addition is 2.01ns. We compare 110nm standard cell post-synthesis results for the reconfigurable arithmetic block to results of synthesis using Look-Up Tables on Xilinx Spartan-3 FPGAs

We present an efficient addition circuit, borrowing techniques from the classical carry-lookahead arithmetic circuit. Our quantum carrylookahead (qcla) adder accepts two n-bit numbers and adds them in O(log n) depth using O(n) ancillary qubits. We present both in-place and out-of-place versions, as well as versions that add modulo 2 n and modulo 2 n − 1. Previously, the linear-depth ripple-carry addition circuit has been the method of choice. Our work reduces the cost of addition dramatically with only a slight increase in the number of required qubits. The qcla adder can be used within current modular multiplication circuits to reduce substantially the run-time of Shor’s algorithm. 1