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Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
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Cited by 117 (32 self)
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This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
Clock Distribution Networks in Synchronous Digital Integrated Circuits
 Proc. IEEE
, 2001
"... this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path ..."
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Cited by 81 (6 self)
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this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path and the clock skew of that path are described in Section IV. The interplay among the aforementioned three subsystems making up a synchronous digital system is described in Section V; particularly, how the timing characteristics of the memory and logic elements constrain the design and synthesis of clock distribution networks. Different forms of clock distribution networks, such as buffered trees and Htrees, are discussed. The automated layout and synthesis of clock distribution networks are described in Section VI. Techniques for making clock distribution networks less sensitive to process parameter variations are discussed in Section VII. Localized scheduling of the clock delays is useful in optimizing the performance of highspeed synchronous circuits. The process for determining the optimal timing characteristics of a clock distribution network is reviewed in Section VIII. The application of clock distribution networks to highspeed circuits has existed for many years. The design of the clock distribution network of certain important VLSIbased systems has been described in the literature, and some examples of these circuits are described in Section IX. In an effort to provide some insight into future and evolving areas of research relevant to highperformance clock distribution networks, some potentially important topics for future research are discussed in Section X. Finally, a summary of this paper with some concluding remarks is provided in Section XI
Reducing Clock Skew Variability via Cross Links
 IN PROCEEDINGS OF THE 41ST ANNUAL CONFERENCE ON DESIGN AUTOMATION
, 2004
"... Increasingly significant variational e#ects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular ..."
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Cited by 40 (8 self)
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Increasingly significant variational e#ects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular structures, and often consume excessive amount of wires. In this paper, we suggest to construct a low cost nontree clock network by inserting cross links in a given clock tree. The e#ect of the link insertion on clock skew variability is analyzed. Based on the analysis, two link insertion schemes are proposed. These methods can quickly convert a clock tree to a nontree with significantly lower skew variability and very small amount of extra wires. Further, they can be applied to the recently popular nonzero skew routing easily. Experimental results on benchmark circuits show that this approach can achieve significant skew variability reduction with less than 2% increase of wirelength.
Hybrid structured clock network construction
 Proceedings of the 2001 IEEE/ACM international conference on Computeraided design
, 2001
"... This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zeroskew clock meshes, with underlying zeroskew clock trees originating from the mesh nodes. We propose a mesh construction procedure, which guarantees zero skew under the Elmore delay model, us ..."
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Cited by 22 (0 self)
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This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zeroskew clock meshes, with underlying zeroskew clock trees originating from the mesh nodes. We propose a mesh construction procedure, which guarantees zero skew under the Elmore delay model, using a simple and efficient linear programming formulation. Buffers are inserted to reduce the transition time (or rise time). As a postprocessing step, wire width optimization under an accurate higherorder delay metric is performed to further minimize the transition time and propagation delay/skew. Experimental results show that the hybrid mesh/tree construction scheme can provide smaller propagation delay and transition time than a comparable clock tree. 1.
MinimumCost BoundedSkew Clock Routing
 IEEE Intl. Symp. Circuits and Systems
, 1995
"... In this paper, we present a new clock routing algorithm which minimizes total wirelength under any given pathlength skew bound. The algorithm constructs a boundedskew tree (BST) in two steps: (i) a bottomup phase to construct a binary tree of shortestdistance feasible regions which represent the ..."
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Cited by 21 (4 self)
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In this paper, we present a new clock routing algorithm which minimizes total wirelength under any given pathlength skew bound. The algorithm constructs a boundedskew tree (BST) in two steps: (i) a bottomup phase to construct a binary tree of shortestdistance feasible regions which represent the loci of possible placements of clock entry points, and (ii) a topdown phase to determine the exact locations of clock entry points. Experimental results show that our clock routing algorithm, named BST/DME, can produce a set of routing solutions with skew and wirelength tradeoff. 1 Introduction Clock skew minimization is an important issue in the design of high performance circuits. Over the past few years, a number of clock routing algorithms have been proposed, including the Htree construction for regular systolic arrays [1], the method of means and medians (MMM) by [10], the recursive geometric matching method by [6], and exact zero skew routing under the Elmore delay model by [17]....
Statistical based link insertion for robust clock network design,” ICCAD
 Proc. of the ICCAD
, 2005
"... We present a statistical based nontree clock distribution construction algorithm that starts with a tree and incrementally insert cross links, such that the skew variation of the final clock network is within a certain confidence interval under variations in wire width. Monte Carlo simulations show ..."
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Cited by 7 (1 self)
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We present a statistical based nontree clock distribution construction algorithm that starts with a tree and incrementally insert cross links, such that the skew variation of the final clock network is within a certain confidence interval under variations in wire width. Monte Carlo simulations show that the robustness of the final clock network can be significantly improved with a small increase in wire length. 1
Improved algorithms for linkbased nontree clock networks for skew variability reduction
 In ISPD ’05: Proceedings of the 2005 international symposium on Physical design
, 2005
"... In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets in any synchronous VLSI chip, the Clock Distribution Network (CDN) is especially sensitive to these variations. Recently p ..."
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Cited by 6 (3 self)
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In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets in any synchronous VLSI chip, the Clock Distribution Network (CDN) is especially sensitive to these variations. Recently proposed linkbased nontree [1] addresses this problem by constructing a nontree that is significantly more tolerant to variations when compared to a clock tree. Although the two algorithms proposed in [1] are effective in reducing the skew variability, they have a few drawbacks including high complexity, lengthy links and uneven link distribution across the clock network. In this paper, we propose two new algorithms that can overcome these disadvantages. The effectiveness of the proposed algorithms has been validated using HSPICE based Monte Carlo simulations. Experimental results show that the new algorithms are able to achieve the same or better skew reduction with an average of 5 % wire length increase when compared to the 15 % wire length increase of the existing algorithms in [1]. Moreover, the new algorithms scale extremely well to big clock networks, i.e., the bigger the clock network, the less overall link cost (less than 2 % for the biggest benchmark we have).
Clock Tree Synthesis for Timing Convergence and Timing Yield . . .
, 2005
"... Designing highperformance very largescale integration (VLSI) chips has become more challenging than ever due to nanometer effects and accelerating timetomarket cycles. Due to the interconnect delay dominance, a small routing change in the design can increase coupling capacitances on its neighbor ..."
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Cited by 1 (0 self)
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Designing highperformance very largescale integration (VLSI) chips has become more challenging than ever due to nanometer effects and accelerating timetomarket cycles. Due to the interconnect delay dominance, a small routing change in the design can increase coupling capacitances on its neighboring paths and significantly increase their path delays. This can cause new timing violations and result in design iterations. While timing convergence is getting harder and harder to achieve, the accelerating timetomarket cycles further aggravate the problem. Process variations result in interconnect variations, threshold voltage variations, leakage power variations, etc. These effects not only generate reliability issues but also make the circuit performance deviate from the design specification and cause timing yield losses. Due to the increasing process variations in nanometer technologies, timing yield has become an important design concern because it directly affects the manufacturing cost. Clock designs have significant impacts on both timing convergence and timing yield. A carefully designed clock distribution network can reduce designinherited clock skews, the discrepancies between designer intended clock skews and achieved clock skews under perfect process conditions. This can improve circuit performance and timing convergence. A clock distribution network can also be optimized
PIII8 ProcessVariation Robust and LowPower ZeroSkew Buffered ClockTree Synthesis Using Projected ScanLine Sampling*
"... jltsaiocae. wisc. edu Abstract Zeroskew clocktree.with minimum clockdelay is preferable due to its low unintentional and processvariation induced skews. We propose a zeroskew buffered clocktree synthesis flow and a novel algorithm that enables clocktree optimization throughout the full zer ..."
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jltsaiocae. wisc. edu Abstract Zeroskew clocktree.with minimum clockdelay is preferable due to its low unintentional and processvariation induced skews. We propose a zeroskew buffered clocktree synthesis flow and a novel algorithm that enables clocktree optimization throughout the full zeroskew designspace by considering simultaneous bufferinsertion, buffersizing, and wiresizing. For an industrial clocktree with 3101 sink nodes, our algorithm,achieves up to 45X clockdelay improvement and up to 23 % power reduction compared with its initial routing. 1.
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis
"... Clock distribution is one of the key limiting factors in any high speed, sub100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, powerground noise etc., consume increasing proportion of the clock cycle. Thus, reducing the clock skew variations is o ..."
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Clock distribution is one of the key limiting factors in any high speed, sub100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, powerground noise etc., consume increasing proportion of the clock cycle. Thus, reducing the clock skew variations is one of the most important objectives of any highspeed clock distribution methodology. Inserting crosslinks in a given clock tree is one way to reduce unwanted clock skew variations [1–6]. However, most of the existing methods like [1–5] use empirical methods and do not use delay/skew variation information to select the links to be inserted. This can result in ineffective links being inserted. The work of [6] considers the delay variation directly, but it is very slow even for small clock trees. In this paper, we propose a fast link insertion algorithm that considers the delay variation information directly during link selection process. Our algorithm inserts links only in the parts of the clock tree that are most susceptible to variation effects by evaluating the skew sensitivity to variations. Another key feature of our algorithm is that it is compatible with any higher order delay model/variation model, unlike the existing algorithms. We verify the effectiveness of our algorithm using HSPICE based Monte Carlo simulations on a set of standard benchmarks. 1.