This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, non-tree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.

Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing algorithms targeting discrete, non-linear, non-unimodal, constrained optimization. The goal is to overcome the non-linearity and nonunimodality of the delay and the power to achieve good quality results within a reasonable CPU time, e.g., handling a 10000 node network in 2 hours. We compare the five algorithms on constraint free delay optimization and delay constrained power optimization, and show that one method is superior to the others. 1 Introduction Early work on gate sizing targeting area/delay optimization can be found in [20, 12]. Using a RC delay model, TILOS [8] expresses the delay and area as posynomials. Geometric programming or heuristics based greedy approaches can be used to so...

A new performance and area optimization algorithm for complex VLSI systems is presented. It is widely believed within the VLSI CAD community that the relationship between delay and silicon area of a VLSI chip is convex. This conclusion is based on a simplified linear RC model to predict gate delays. In the proposed optimization algorithm, a nonlinear, non-RC based transistor delay model was used which resulted in a non-convex relationship between the delay and the silicon area of a VLSI chip. Genetic algorithms are better suited for discrete, non-convex, non-linear optimization problems than traditional calculus-based algorithms. By using the genetic algorithms in the performance and area optimization, we are able to find the optimal values for both delay and silicon area for the ISCAS benchmark circuits. Key Words: Area and Performance optimization; Transistor Sizing; Genetic algorithms 1 Introduction The techniques for performance and area optimization of VLSI systems can be divi...