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49
Compositional Model Checking
, 1999
"... We describe a method for reducing the complexity of temporal logic model checking in systems composed of many parallel processes. The goal is to check properties of the components of a system and then deduce global properties from these local properties. The main difficulty with this type of approac ..."
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Cited by 2407 (62 self)
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We describe a method for reducing the complexity of temporal logic model checking in systems composed of many parallel processes. The goal is to check properties of the components of a system and then deduce global properties from these local properties. The main difficulty with this type of approach is that local properties are often not preserved at the global level. We present a general framework for using additional interface processes to model the environment for a component. These interface processes are typically much simpler than the full environment of the component. By composing a component with its interface processes and then checking properties of this composition, we can guarantee that these properties will be preserved at the global level. We give two example compositional systems based on the logic CTL*.
Automatic verification of finitestate concurrent systems using temporal logic specifications
 ACM Transactions on Programming Languages and Systems
, 1986
"... We give an efficient procedure for verifying that a finitestate concurrent system meets a specification expressed in a (propositional, branchingtime) temporal logic. Our algorithm has complexity linear in both the size of the specification and the size of the global state graph for the concurrent ..."
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Cited by 1173 (58 self)
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We give an efficient procedure for verifying that a finitestate concurrent system meets a specification expressed in a (propositional, branchingtime) temporal logic. Our algorithm has complexity linear in both the size of the specification and the size of the global state graph for the concurrent system. We also show how this approach can be adapted to handle fairness. We argue that our technique can provide a practical alternative to manual proof construction or use of a mechanical theorem prover for verifying many finitestate concurrent systems. Experimental results show that state machines with several hundred states can be checked in a matter of seconds.
Logic in Computer Science: Modelling and Reasoning about Systems
, 1999
"... ion. ACM Transactions on Programming Languages and Systems, 16(5):15121542, September 1994. Bibliography 401 [Che80] B. F. Chellas. Modal Logic  an Introduction. Cambridge University Press, 1980. [Dam96] D. R. Dams. Abstract Interpretation and Partition Refinement for Model Checking. PhD thesi ..."
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Cited by 238 (8 self)
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ion. ACM Transactions on Programming Languages and Systems, 16(5):15121542, September 1994. Bibliography 401 [Che80] B. F. Chellas. Modal Logic  an Introduction. Cambridge University Press, 1980. [Dam96] D. R. Dams. Abstract Interpretation and Partition Refinement for Model Checking. PhD thesis, Institute for Programming research and Algorithmics. Eindhoven University of Technology, July 1996. [Dij76] E. W. Dijkstra. A Discipline of Programming. Prentice Hall, 1976. [DP96] R. Davies and F. Pfenning. A Modal Analysis of Staged Computation. In 23rd Annual ACM Symposium on Principles of Programming Languages. ACM Press, January 1996. [EN94] R. Elmasri and S. B. Navathe. Fundamentals of Database Systems. Benjamin/Cummings, 1994. [FHMV95] Ronald Fagin, Joseph Y. Halpern, Yoram Moses, and Moshe Y. Vardi. Reasoning about Knowledge. MIT Press, Cambridge, 1995. [Fit93] M. Fitting. Basic modal logic. In D. Gabbay, C. Hogger, and J. Robinson, editors, Handbook of Logic in Artificial In...
Bounded Model Checking Using Satisfiability Solving
 Formal Methods in System Design
, 2001
"... The phrase model checking refers to algorithms for exploring the state space of a transition system to determine if it obeys a specification of its intended behavior. These algorithms can perform exhaustive verification in a highly automatic manner, and, thus, have attracted much interest in indus ..."
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Cited by 139 (1 self)
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The phrase model checking refers to algorithms for exploring the state space of a transition system to determine if it obeys a specification of its intended behavior. These algorithms can perform exhaustive verification in a highly automatic manner, and, thus, have attracted much interest in industry. Model checking programs are now being commercially marketed. However, model checking has been held back by the state explosion problem, which is the problem that the number of states in a system grows exponentially in the number of system components. Much research has been devoted to ameliorating this problem.
Verification Tools for FiniteState Concurrent Systems
"... Temporal logic model checking is an automatic technique for verifying finitestate concurrent systems. Specifications are expressed in a propositional temporal logic, and the concurrent system is modeled as a statetransition graph. An efficient search procedure is used to determine whether or not t ..."
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Cited by 118 (3 self)
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Temporal logic model checking is an automatic technique for verifying finitestate concurrent systems. Specifications are expressed in a propositional temporal logic, and the concurrent system is modeled as a statetransition graph. An efficient search procedure is used to determine whether or not the statetransition graph satisfies the specification. When the technique was first developed ten years ago, it was only possible to handle concurrent systems with a few thousand states. In the last few years, however, the size of the concurrent systems that can be handled has increased dramatically. By representing transition relations and sets of states implicitly using binary decision diagrams, it is now possible to check concurrent systems with more than 10 120 states. In this paper we describe in detail how the new implementation works and
Verification of the Futurebus+ Cache Coherence Protocol
, 1995
"... We used a hardware description language to construct a formal model of the cache coherence protocol described in the IEEE Futurebus+ standard. By applying temporal logic model checking techniques, we found errors in the standard. The result of our project is a concise, comprehensible and unambiguous ..."
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Cited by 94 (15 self)
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We used a hardware description language to construct a formal model of the cache coherence protocol described in the IEEE Futurebus+ standard. By applying temporal logic model checking techniques, we found errors in the standard. The result of our project is a concise, comprehensible and unambiguous model of the protocol that should be useful both to the Futurebus+ Working Group members, who are responsible for the protocol, and to actual designers of Futurebus+ boards.
Symbolic Verification of Communication Protocols with Infinite State Spaces using QDDs (Extended Abstract)
 In CAV'96. LNCS 1102
"... ) Bernard Boigelot Universit'e de Li`ege Institut Montefiore, B28 4000 Li`ege SartTilman, Belgium Email: boigelot@montefiore.ulg.ac.be Patrice Godefroid Lucent Technologies  Bell Laboratories 1000 E. Warrenville Road Naperville, IL 60566, U.S.A. Email: god@belllabs.com Abstract We study the v ..."
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Cited by 83 (7 self)
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) Bernard Boigelot Universit'e de Li`ege Institut Montefiore, B28 4000 Li`ege SartTilman, Belgium Email: boigelot@montefiore.ulg.ac.be Patrice Godefroid Lucent Technologies  Bell Laboratories 1000 E. Warrenville Road Naperville, IL 60566, U.S.A. Email: god@belllabs.com Abstract We study the verification of properties of communication protocols modeled by a finite set of finitestate machines that communicate by exchanging messages via unbounded FIFO queues. It is wellknown that most interesting verification problems, such as deadlock detection, are undecidable for this class of systems. However, in practice, these verification problems may very well turn out to be decidable for a subclass containing most "real" protocols. Motivated by this optimistic (and, we claim, realistic) observation, we present an algorithm that may construct a finite and exact representation of the state space of a communication protocol, even if this state space is infinite. Our algorithm performs a loo...
Memoryefficient algorithms for the verification of temporal properties
 FORMAL METHODS IN SYSTEM DESIGN
, 1992
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Verifying Safety Properties of a PowerPC Microprocessor Using Symbolic Model Checking without BDDs
 In Proc. 11 th Int. Conf. on Computer Aided Verification
, 1999
"... . In [1] Bounded Model Checking with the aid of satisfiability solving (SAT) was introduced as an alternative to symbolic model checking with BDDs. In this paper we show how bounded model checking can take advantage of specialized optimizations. We present a bounded version of the cone of influe ..."
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Cited by 50 (10 self)
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. In [1] Bounded Model Checking with the aid of satisfiability solving (SAT) was introduced as an alternative to symbolic model checking with BDDs. In this paper we show how bounded model checking can take advantage of specialized optimizations. We present a bounded version of the cone of influence reduction. We have successfully applied this idea in checking safety properties of a PowerPC microprocessor at Motorola 's Somerset PowerPC design center. Based on that experience, we propose a verification methodology that we feel can bring model checking into the mainstream of industrial chip design. 1 Introduction Model checking has only been partially accepted by industry as a supplement to traditional verification techniques. The reason is that model checking, which, to date, has been based on BDDs or on explicit state graph exploration, has not been robust enough for industry. Model checking [3, 12] was first proposed as a verification technique eighteen years ago. However, ...
Verifying Parameterized Networks using Abstraction and Regular Languages
, 1995
"... ion and Regular Languages ? E. M. Clarke 1 and O. Grumberg 2 and S. Jha 1 1 Carnegie Mellon University, Pittsburgh, PA 15213 2 Computer Science Dept, The Technion, Haifa 32000, Israel Abstract. This paper describes a technique based on network grammars and abstraction to verify families of ..."
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Cited by 47 (0 self)
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ion and Regular Languages ? E. M. Clarke 1 and O. Grumberg 2 and S. Jha 1 1 Carnegie Mellon University, Pittsburgh, PA 15213 2 Computer Science Dept, The Technion, Haifa 32000, Israel Abstract. This paper describes a technique based on network grammars and abstraction to verify families of statetransition systems. The family of statetransition systems is represented by a contextfree network grammar. Using the structure of the network grammar our technique constructs an invariant which simulates all the statetransition systems in the family. A novel idea used in this paper is to use regular languages to express state properties. We have implemented our techniques and verified two nontrivial examples. 1 Introduction Automatic verification of statetransition systems using temporal logic model checking has been investigated by numerous authors [3, 4, 5, 12, 16]. The basic model checking problem is easy to state Given a statetransition system P and a temporal formula f , de...