Retiming is a well known technique for sequential circuit optimization originally proposed by Leiserson and Saxe [LeRS83, LeSa91]. For designs with given initial states, however, new equivalent initial states must be computed for retiming, which unfortunately is NP-hard. In this paper we propose a novel polynomial time algorithm for optimal FPGA mapping with forward retiming to minimize the clock period with guaranteed initial state computation. It enables a new methodology of separating forward retiming from backward retiming to avoid timeconsuming iterations between retiming and initial state computation. Comparing with the clock period computed by our algorithm, the clock period by conventional approaches of separate mapping followed by retiming [CoDi94, LeSa91] is 20.2% larger, but the clock period by recent approaches of optimal mapping with retiming [PaLi96, PaLi99, CoWu96a] is 2.8% smaller. However, many of the optimal mapping with retiming solutions by [PaLi96, PaLi99, CoWu96a] cannot compute an equivalent initial state by SIS [SeSL92] based on the state-of-the-art algorithm of equivalent initial state computation for retiming in [ToBr93]. Our approach is also applicable to circuits with partial initial state assignment. 1

An algorithm for unifying the techniques of gate sizing and clockskew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycle-borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. Experimental results verify that cycle-borrowing using sizing+skew results in a better overall area-delay tradeoff than with sizing alone.

This paper analyzes the effect of resource sharing and assignment on the clock period of the synthesized circuit. The assignment phase assigns or binds operations of the scheduled behavioral description to a set of allocated resources. We focus on control-flow intensive descriptions, characterized by the presence of mutually exclusive paths due to the presence of nested conditional branches and loops. We show that

Implicit reachable state computation can be applied to a wide range of sequential formal verification and logic synthesis problems. Symbolic manipulation with BDDs is one of the most efficient techniques known for the reachability analysis. The technique was first proposed by Coudert et al. in 1989, and was improved later by Touati et al. in 1990. The standard approach chooses the cut of a sequential circuit which consists of the output of all the latches. Choosing a valid cut different from the original one will change the complexity of the reachability analysis. Also the reachability information of the retimed circuit is always possible to be transformed back to that of the original circuit with the standard cut. This project explored the circuit retiming for improving the reachability analysis.