A software energy estimation methodology is presented that avoids explicit characterization of instruction energy consumption and predicts energy consumption to within 3 % accuracy for a set of benchmark programs evaluated on the StrongARM SA-1100 and Hitachi SH-4 microprocessors. The tool, JouleTrack, is available as an online resource and has various estimation levels. It also isolates the switching and leakage components of the energy consumption.

Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been veri ed by HSPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50 % for some circuits.

Reduction in leakage power has become an important concern in lowvoltage, lowpower and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using lowthreshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been veri#ed by HSPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50#. 1 Introduction With the growing use of portable and wireless electronic systems, reduction in power consumption has become more and more importantintoday's VLSI circuit and system designs #1#, ...

In emerging embedded applications such as wireless sensor networks, the key metric is minimizing energy dissipation rather than processor speed. Minimum energy analysis of CMOS circuits estimates the optimal operating point of clock frequencies, supply voltage, and threshold voltage [1]. The minimum energy analysis shows that the optimal power supply typically occurs in subthreshold (e.g., supply voltages are below device thresholds). New subthreshold logic and memory design methodologies are developed and demonstrated on a fast Fourier transform (FFT) processor. The FFT processor uses an energy-aware architecture that allows for variable FFT length (128--1024 point), variable bit-precision (8 b and 16 b) and is designed to investigate the estimated minimum energy point. The FFT processor is fabricated using a standard 0.18- mCMOS logic process and operates down to 180 mV. The minimum energy point for the 16-b 1024-point FFT processor occurs at 350-mV supply voltage where it dissipates 155 nJ/FFT at a clock frequency of 10 kHz.

Lowering during standby mode reduces power by decreasing both voltage and current. Analysis of flip-flop structures shows how low the voltage can scale before destroying the state information. Measurements of a 0.13- m, dual--- test chip show that reducing to near the point where state is lost gives the best power savings. We show that "canary" flip-flops provide a mechanism for observing the proximity to failure for the flip-flops. The canary flip-flops enable closed-loop standby voltage scaling for achieving savings near the optimum. This approach potentially provides over 2 higher savings than an optimal open-loop approach without loss of state.

Automatic Synthesis of CMOS Digital/Analog Converters by Robert McKinstry Robinson Neff Doctor of Philosophy in Engineering -- Electrical Engineering and Computer Sciences University of California at Berkeley Professor Paul R. Gray, Chair Synthesis of analog functional blocks in integrated circuits offers promise for improved designer productivity. By developing module generators for commonly used analog circuit elements, a synthesis methodology may be matched to a particular application, with approaches and algorithms determined by the particular needs of target circuit type. An analog circuit designer should be able to input design specifications and underlying technology information, and a synthesis methodology should determine circuit parameter values and dimensions, creating the required mask layouts. Slow, tedious design and redesign methods should be replaced by one in which the computer finds minimum cost designs which meet performance requirements. This work implements synthesis methods for a widely used analog block, the digital/analog converter (DAC).

This paper presents a novel approach for leakage optimization through simultanous Vt selection and assignment. Vt selection implies deciding the right value for Vt and assignment implies deciding which gates should be assigned which thresh-hold value. The proposed algorithm is a general mathematical formulation that can be trivially extended to multiple thresh-hold voltages (more than two). Traditional leakage optimization strategies either assume the prespecification of thresh-hold values or are good only for two threshholds. The presented formulation is based on linear programming approach under the piecewise linear approximation of delay/leakage vs thresh-hold curves. The algortihm was incorporated in SIS. Experimental results indicate that on some benchmarks having more that two thresh-holds was beneficial for leakage.

Development of the process technology for dual threshold (dual V th ) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance circuits. It has been demonstrated that by using transistors of a low threshold voltage for gates on the critical path, and by using a high threshold voltage for gates in the off-critical path it is possible to significantly reduce leakage power consumption of a circuit without performance degradation. In this paper we have proposed a new algorithm to realize dual threshold CMOS circuits. Our algorithm produces significantly better results for the ISCAS benchmark circuits compared to the reported results.

An approach is presented for the analysis of the nonlinear behavior of analog integrated circuits. The approach is based on a variant of the Volterra series approach for frequencydomain analysis of weakly nonlinear circuits with one input port, such as amplifiers, and with more than one input port, such as analog mixers and multipliers. By coupling numerical results with symbolic results, both obtained with this method, insight into the nonlinear operation of analog integrated circuits can be gained. For accurate distortion computations, the accuracy of the transistor models is critical. A MOS transistor model is discussed that allows us to explain the measured fourth-order nonlinear behavior of a 1-GHz CMOS upconverter. Further, the method is illustrated with several examples, including the analysis of an operational amplifier up to its gain-bandwidth product. This example has also been verified experimentally. Index Terms---Analog integrated circuits, harmonic distortion, nonlinear ...

Coupling effect due to line-to-line capacitance is of serious concern in timing analysis of circuits in ultra deep submicron CMOS technology. Often coupling delay is strongly dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual V t technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low V t is applied properly.