This paper presents a flexible and efficient approach to evaluating implications as well as deriving indirect implications in logic circuits. Evaluation and derivation of implications are essential in ATPG, equivalence checking, and netlist optimization. Contrary to other methods, our approach is based on a graph model of a circuit's clause description called implication graph. It combines both the flexibility of SAT-based techniques and high efficiency of structure based methods. As the proposed algorithms operate only on the implication graph, they are independent of the chosen logic. Evaluation of implications and computation of indirect implications are performed by simple and efficient graph algorithms. Experimental results for various applications relying on implication demonstrate the effectiveness of our approach. 1 Introduction Recently, substantial progress has been achieved in the fields of Boolean equivalence checking and optimization of netlists. Techniques for deriving ...

We analyze all signals of a combinational circuit simultaneously for redundancy. The state of a signal is represented by two binary variables. The first variable is the logic value of the signal. The second variable is the observability status of the signal with respect to all primary outputs. Boolean equations specify local relationships of these variables in a manner similar to the neural network or Boolean satisfiability method. All pairwise terms appearing in these Boolean equations are used to construct an implication graph, for which the transitive closure graph is obtained. Any signal assignments or relations found from the transitive closure are substituted into higher-order terms of the Boolean equations, some of which reduce to pairwise terms. Such cases are iteratively included in the transitive closure until no more reductions are possible. In the final transitive closure, all signals are examined for the following conditions of redundancy: (1) If a signal and its complement imply each other (contradiction) then both stuck-at faults on that signal are redundant; (2) If one value implies the other value (fixation) then one of the stuck-at faults on that signal is redundant; (3) If the true observability status of a signal implies its own false observability status, then both stuck-at faults of that signal are redundant; (4) If a certain value of a signal implies the false observability status, then the corresponding stuck-at fault is redundant. Despite the apparent similarities with the transitive closure based ATPG, the present method is quite different. Here transitive closure is computed just once, and not recomputed or updated separately for each fault as required in ATPG. We give ISCAS '85 benchmark results. For c6288, we could identify 31 out of 33 redu...

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This paper presents a flexible and efficient approach to evaluating implications as well as deriving indirect implications in logic circuits. Evaluation and derivation of implications are essential in ATPG, equivalence checking, and netlist optimization. Contrary to other methods, our approach is based on a graph model of a circuit's clause description called the implication graph. It combines both the flexibility of SAT-based techniques and high efficiency of structure based methods. As the proposed algorithms operate only on the implication graph, they are independent of the chosen logic. Evaluation of implications and computation of indirect implications are performed by simple and efficient graph algorithms. Experimental results for various applications relying on implication demonstrate the efficiency of our approach. 1 Introduction Recently, substantial progress has been achieved in the fields of Boolean equivalence checking and optimization of netlists. Techniques for deriv...

Redundant logic in a digital circuit is often identified as untestable or redundant single stuck-at faults. Redundant faults in a combinational circuit are faults that no input patterns can detect [2]. Removal of such faults simplifies the circuit without chang\Lambda Student

This paper presents a flexible and efficient approach to deriving indirect implications in logic circuits. Indirect implications are essential in ATPG, equivalence checking, and netlist optimization. Contrary to other methods, our approach is based on a graph model of a circuit's clause description called the implication graph. It combines both the flexibility of SAT-based techniques and high efficiency of structure based methods. As the proposed algorithms operate only on the implication graph, they are independent of the chosen logic. Computation of indirect implications is performed by simple and efficient graph algorithms. Experimental results for various applications relying on indirect implications demonstrate the efficiency of our approach. 1 INTRODUCTION Recently, substantial progress has been achieved in the fields of Boolean equivalence checking and optimization of netlists. Techniques for deriving indirect implications, which were originally developed for ATPG tools, play...

There is a class of implication-based methods that identify logic redundancy from circuit topology and without any primary input assignment. These methods are less complex than automatic test pattern generation (ATPG) but identify only a subset of all redundancies. This paper provides new results to enlarge this subset. Contributions are a fixed-value theorem and two theorems on fanout stem unobservability. We represent signal controllabilities and observabilities using an implication graph and its transitive closure (TC). Both complete and partial implications are included. Weaknesses of this procedure areindealing with the e ects of xedvalued variables on TC and the lack of observability relations across fanouts. The xed-value theorem adds unconditional edges from all variables to the xed variable and then recomputes TC recursively until no new fixed nodes are found. The stem unobservability theorems determine the observability status of a fanout stem from its dominator set, which either has fixed values, or is unobservable. Results are considerably improved from the previously reported implication-based identi ers. In the c5315 circuit we identify 58 out of 59 redundant faults. All 34 redundant faults of c6288 are identified.