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A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets
, 2002
"... Nodes in a dominance graph represent faults of a circuit. A directed edge from node fi to node fj means that fault fj dominates fi. The equivalence of faults fi and fj is indicated by the presence of simultaneous edges fi! fj and fj! fi. When local dominance and equivalence relations are included in ..."
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Cited by 18 (4 self)
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Nodes in a dominance graph represent faults of a circuit. A directed edge from node fi to node fj means that fault fj dominates fi. The equivalence of faults fi and fj is indicated by the presence of simultaneous edges fi! fj and fj! fi. When local dominance and equivalence relations are included in this graph, its transitive closure provides the collapsed fault sets. Precollapsed fault sets of standard cells and other logic blocks can be stored in a graph library for hierarchical fault collapsing. Examples show how more compact fault sets are obtained by using functional equivalences that can be found by analysis of small cells. Benchmark circuits c432 and c499 are used to illustrate the use of functional fault collapsing within their exclusiveOR cells.
A FaultIndependent Transitive Closure Algorithm for Redundancy Identification
 IN PROC. OF THE 16 TH INTERNATIONAL CONF. VLSI DESIGN
, 2003
"... We present a faultindependent redundancy identification algorithm. The controllabilities and observabilities are defined as Boolean variables and represented on an implication graph. A major enhancement over previously published results is that we include all direct and partial implications, as we ..."
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Cited by 8 (5 self)
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We present a faultindependent redundancy identification algorithm. The controllabilities and observabilities are defined as Boolean variables and represented on an implication graph. A major enhancement over previously published results is that we include all direct and partial implications, as well as node fixation. The transitive closure, whose computation now requires a new algorithm, provides many redundant faults in a singlepass analysis. Because of these improvements, we obtain better performance than all previous faultindependent methods at execution speeds that are much faster than any exhaustive ATPG. For example, in the s9234 circuit more than half of the redundant faults are found in just 14 seconds on a Sparc 5. All 34 redundant faults of c6288 are found in one pass. Besides, our single pass procedure can classify faults according to the causes of their redundancy. The weakness of our method, as we illustrate by examples, lies in the lack of a formulation for the observabilities of fanout stems.
Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies
 Proc. 18 th International Conf. VLSI Design
, 2005
"... Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used ..."
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Cited by 3 (1 self)
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Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used “anding ” node. An ninput gate requires one oring and one anding nodes to represent all partial implications. This implication graph is shown to be more complete and more compact compared to the previously published (n+1) anding node graph. Introduction of the new oring node finds more redundancies using the transitive closure method. The second contribution of the present work is a set of new algorithms to update transitive closure for every newly added edge in the implication
Using Contrapositives to Enhance the Implication Graph of Logic Circuits
 in Proc. of the 13 th IEEE North Atalantic Test Workshop
, 2004
"... Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used ..."
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Cited by 1 (1 self)
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Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used “anding ” node. The addition of a single oring node in the implication graph of a Boolean gate eliminates the need for several anding nodes. An ninput gate requires one oring and one anding nodes to represent all partial implications. This implication graph is shown to be more complete and more compact compared to the previously published (n+1) anding nodes graph. Introduction of the new oring node finds more redundancies using the transitive closure method. The second contribution of the present work is new algorithms
Theorems on Redundancy Identification
 in Proc. of the 12th North Atlantic Test Workshop
, 2003
"... Redundant logic in a digital circuit is often identified as untestable or redundant single stuckat faults. Redundant faults in a combinational circuit are faults that no input patterns can detect [2]. Removal of such faults simplifies the circuit without chang\Lambda Student ..."
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Cited by 1 (0 self)
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Redundant logic in a digital circuit is often identified as untestable or redundant single stuckat faults. Redundant faults in a combinational circuit are faults that no input patterns can detect [2]. Removal of such faults simplifies the circuit without chang\Lambda Student
FixedValue and Stem Unobservability Theorems for Logic Redundancy Identification
, 2003
"... There is a class of implicationbased methods that identify logic redundancy from circuit topology and without any primary input assignment. These methods are less complex than automatic test pattern generation (ATPG) but identify only a subset of all redundancies. This paper provides new results to ..."
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There is a class of implicationbased methods that identify logic redundancy from circuit topology and without any primary input assignment. These methods are less complex than automatic test pattern generation (ATPG) but identify only a subset of all redundancies. This paper provides new results to enlarge this subset. Contributions are a fixedvalue theorem and two theorems on fanout stem unobservability. We represent signal controllabilities and observabilities using an implication graph and its transitive closure (TC). Both complete and partial implications are included. Weaknesses of this procedure areindealing with the e ects of xedvalued variables on TC and the lack of observability relations across fanouts. The xedvalue theorem adds unconditional edges from all variables to the xed variable and then recomputes TC recursively until no new fixed nodes are found. The stem unobservability theorems determine the observability status of a fanout stem from its dominator set, which either has fixed values, or is unobservable. Results are considerably improved from the previously reported implicationbased identi ers. In the c5315 circuit we identify 58 out of 59 redundant faults. All 34 redundant faults of c6288 are identified.