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162
Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
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Cited by 109 (32 self)
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This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
Kahng A B, Zero skew clock routing with minimum wirelength
 Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
, 1992
"... ..."
Clock Distribution Networks in Synchronous Digital Integrated Circuits
 Proc. IEEE
, 2001
"... this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path ..."
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Cited by 63 (5 self)
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this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path and the clock skew of that path are described in Section IV. The interplay among the aforementioned three subsystems making up a synchronous digital system is described in Section V; particularly, how the timing characteristics of the memory and logic elements constrain the design and synthesis of clock distribution networks. Different forms of clock distribution networks, such as buffered trees and Htrees, are discussed. The automated layout and synthesis of clock distribution networks are described in Section VI. Techniques for making clock distribution networks less sensitive to process parameter variations are discussed in Section VII. Localized scheduling of the clock delays is useful in optimizing the performance of highspeed synchronous circuits. The process for determining the optimal timing characteristics of a clock distribution network is reviewed in Section VIII. The application of clock distribution networks to highspeed circuits has existed for many years. The design of the clock distribution network of certain important VLSIbased systems has been described in the literature, and some examples of these circuits are described in Section IX. In an effort to provide some insight into future and evolving areas of research relevant to highperformance clock distribution networks, some potentially important topics for future research are discussed in Section X. Finally, a summary of this paper with some concluding remarks is provided in Section XI
Optimizing TwoPhase, LevelClocked Circuitry (Extended Abstract)
"... We investigate two strategies for reducing the clock period of a twophase, levelclocked circuit: clock tuning, which adjusts the waveforms that clock the circuit, and retiming, which relocates circuit latches. These methods can be used to convert a circuit with edgetriggered latches into a faster ..."
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Cited by 57 (16 self)
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We investigate two strategies for reducing the clock period of a twophase, levelclocked circuit: clock tuning, which adjusts the waveforms that clock the circuit, and retiming, which relocates circuit latches. These methods can be used to convert a circuit with edgetriggered latches into a faster levelclocked one. We model a twophase circuit as a graph whose vertex set V is a collection of combinational logic blocks, and whose edge set E is a set of interconnections. Each interconnection passes through 0 or more latches, where each latch is clocked by one of two periodic, nonoverlapping waveforms, or phases. We give efficient polynomialtime algorithms for problems involving the timing verification and optimization of twophase circuitry. Included are algorithms for ffl verifyi...
Clocking Design and Analysis for a 600MHz Alpha Microprocessor
 IEEE Journal of Solid State Circuits, Vol
, 1998
"... ..."
Wavepipelining: A tutorial and research survey
 IEEE TRANS. ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
, 1998
"... Wavepipelining is a method of highperformance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of highperformance integrated circuit (IC) technologies, pipelined architectures, and sophisticated computeraided design (CAD) t ..."
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Cited by 49 (0 self)
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Wavepipelining is a method of highperformance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of highperformance integrated circuit (IC) technologies, pipelined architectures, and sophisticated computeraided design (CAD) tools has converted wavepipelining from a theoretical oddity into a realistic, although challenging, VLSI design method. This paper presents a tutorial of the principles of wavepipelining and a survey of wavepipelined VLSI chips and CAD tools for the synthesis and analysis of wavepipelined circuits.
A Graphtheoretic Approach to ClockSkew Optimization
 In Proc. International Symp. on Circuits and Systems
, 1994
"... This paper addresses the problem of minimizing the clock period of a circuit by optimizing the clockskews. We incorporate uncertainty factors and present a formulation that ensures that the optimization will be safe. In (1), the problem of clock period optimization is formulated as a linear program. ..."
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Cited by 45 (3 self)
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This paper addresses the problem of minimizing the clock period of a circuit by optimizing the clockskews. We incorporate uncertainty factors and present a formulation that ensures that the optimization will be safe. In (1), the problem of clock period optimization is formulated as a linear program. We first propose an efficient graphbased solution that takes advantage of the structure of the problem. We also show that the results of (1) may result in exceedingly large skews, and propose a method to reduce these skews without sacrificing the optimality of the clock period. Experimental results on several ISCAS89 benchmark circuits are provided.
Optimal Clock Skew Scheduling Tolerant to Process Variations
, 1996
"... A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSIbased clock distribution networks. This methodology emphasizes the use of nonzero clock skew to reduce the systemwide minimum clock period. Although choosing (or sc ..."
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Cited by 41 (9 self)
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A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSIbased clock distribution networks. This methodology emphasizes the use of nonzero clock skew to reduce the systemwide minimum clock period. Although choosing (or scheduling) clock skew values has been previously recognized as an optimization technique for reducing the minimum clock period, difficulty in controlling the delays of the clock paths due to process parameter variations has limited its effectiveness. In this paper the minimum clock period is reduced using intentional clock skew by calculating a permissible clock skew range for each local data path while incorporating process dependent delay values of the clock signal paths.
ReCycle: Pipeline adaptation to tolerate process variation, ISCA ’07
 Proc. 34th Annual International Symposium on IPSJ Transactions on System LSI Design Methodology Vol. 3 1–21 (Aug. 2010) c© 2010 Information Processing Society of Japan 19 Design and Runtime Reliabilityat the Electronic System Level Computer Architecture,
, 2007
"... Process variation affects processor pipelines by making some stages slower and others faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by the pipeline. To improve performance, this paper proposes ReCycle, an architectural framework that comprehensively applie ..."
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Cited by 39 (6 self)
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Process variation affects processor pipelines by making some stages slower and others faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by the pipeline. To improve performance, this paper proposes ReCycle, an architectural framework that comprehensively applies cycle time stealing to the pipeline — transferring the time slack of the faster stages to the slow ones by skewing clock arrival times to latching elements after fabrication. As a result, the pipeline can be clocked with a period close to the average stage delay rather than the longest one. In addition, ReCycle’s frequency gains are enhanced with Donor stages, which are empty stages added to “donate ” slack to the slow stages. Finally, ReCycle can also convert slack into power reductions. For a 17FO4 pipeline, ReCycle increases the frequency by 12% and the application performance by 9 % on average. Combining ReCycle and donor stages delivers improvements of 36 % in frequency and 15 % in performance on average, completely reclaiming the performance losses due to variation.
Scheduling And Behavioral Transformations For Parallel Systems
, 1993
"... In a parallel system, either a VLSI architecture in hardware or a parallel program in software, the quality of the final design depends on the ability of a synthesis system to exploit the parallelism hidden in the input description of applications. Since iterative or recursive algorithms are usually ..."
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Cited by 39 (3 self)
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In a parallel system, either a VLSI architecture in hardware or a parallel program in software, the quality of the final design depends on the ability of a synthesis system to exploit the parallelism hidden in the input description of applications. Since iterative or recursive algorithms are usually the most timecritical parts of an application, the parallelism embedded in the repetitive pattern of an iterative algorithm needs to be explored. This thesis studies techniques and algorithms to expose the parallelism in an iterative algorithm so that the designer can find an implementation achieving a desired execution rate. In particular, the objective is to find an efficient schedule to be executed iteratively. A form of dataflow graphs is used to model the iterative part of an application, e.g. a digital signal filter or the while/for loop of a program. Nodes in the graph represent operations to be performed and edges represent both intraiteration and interiteration precedence relat...