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DFT for Digital Detection of Analog Parametric Faults in SC Filters
, 2000
"... Parametric faults are a significant cause of incorrect operation in analog circuits. Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration in which it is use ..."
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Parametric faults are a significant cause of incorrect operation in analog circuits. Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration in which it is used. We present a design for test (DFT) scheme that offers the accuracy needed to test highquality circuits. The DFT scheme is based on a circuit that digitally measures the ratio of a pair of capacitors. The circuit is used to characterize the transfer function of a switched capacitor circuit, which is usually determined by capacitor ratios. In our DFT scheme, capacitor ratios can be measured to within 0.01% accuracy and filter parameters can be shown to be satisfied to within 0.1% accuracy. With this characterization process, a filter can be directly shown to satisfy all specifications that depend on capacitor ratios. We believe the accuracy of our approach is at least an order of magnitude...
A CAD Methodology for Switched Current Analogue IP Cores 1
, 2003
"... Current technology allows for the integration of complete systems onto a single chip. These systems on chip (SoC) are increasingly designed by connecting together large predesigned and verified modules, called cores, with the advantage being a faster design cycle. The development of third party Int ..."
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Current technology allows for the integration of complete systems onto a single chip. These systems on chip (SoC) are increasingly designed by connecting together large predesigned and verified modules, called cores, with the advantage being a faster design cycle. The development of third party Intellectual Property (IP) cores is a rapidly expanding industry, and whereas initially these were nearly all digital, analogue IP cores are now representing a greater proportion of this market. In this report we consider issues which should be addressed when designing analogue IP cores, from lowlevel circuit realisations to high level design methodologies. The switched current (SI) technique can implement analogue functions on the most basic of digital processes and further advantages of high speed and low voltage operation, suggest that this may be particularly suitable for implementing analogue IP cores. In this work, we have considered the design of analogue SI filter cores, these being a fundamental analogue building block. The wave filter design technique has been found particularly suitable as a filter design method as it is easily implemented in SI and the
Analog Fault Detection based on Statistical Analysis
, 2000
"... In analog circuits, process variations result in physical parameter variations. Simulated values must then be considered with there tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either '0' or '1' such that we can decide without ambiguity whether a fault is d ..."
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In analog circuits, process variations result in physical parameter variations. Simulated values must then be considered with there tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either '0' or '1' such that we can decide without ambiguity whether a fault is detectable or not, for analog circuits the fault detectability is a vague problem as the fault can either be completely detectable, partially detectable or completely undetectable which makes it very difficult to take a decision. In order to solve this decision problem, we have introduced the probability to detect fault (PDF) function which allows to formalize the problem of analog fault detection under parameter variations.
FDP: Fault Detection Probability Function For Analog Circuits
, 2001
"... In analog integrated circuits, process variations result in physical parameter variations. Simulated performance values must then be considered with their tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either '0' or '1' such that we can decide without ambigui ..."
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In analog integrated circuits, process variations result in physical parameter variations. Simulated performance values must then be considered with their tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either '0' or '1' such that we can decide without ambiguity whether a fault is detectable or not, for analog circuits fault detectability is still a vague problem since the fault can either be completely detectable, partially detectable or completely undetectable which makes it very difficult to take a decision. In order to solve this decision problem, we have introduced the fault detection probability (FDP) function which allows to formalize the problem of analog fault detection subjected to parameter variations.
Evaluating the Digital Fault Coverage for a MixedSignal BuiltIn SelfTest
, 2011
"... This thesis focuses on a digital Builtin SelfTest (BIST) approach to perform specification oriented testing of the analog portion of a mixedsignal system. The BIST utilizes a direct digital synthesizer (DDS) based test pattern generator (TPG) and a multiplieraccumulator (MAC) based output respons ..."
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This thesis focuses on a digital Builtin SelfTest (BIST) approach to perform specification oriented testing of the analog portion of a mixedsignal system. The BIST utilizes a direct digital synthesizer (DDS) based test pattern generator (TPG) and a multiplieraccumulator (MAC) based output response analyzer (ORA) to stimulate and analyze the analog devices under test, respectively. This approach uses the digitaltoanalog converter (DAC) and the analogtodigital converter (ADC), which typically already exist in a mixed signal circuits, to connect the digital BIST circuitry to the analog device(s) under test (DUT). Previous work has improved and analyzed the capabilities and effectiveness of using this BIST approach to test analog circuitry; however, little work has been done to determine the fault coverage of the digital BIST circuitry itself. Traditionally additional test circuitry dedicated to testing would be added to the BIST circuitry to provide adequate fault coverage of digital circuitry. While ensuring that the digital circuitry is thoroughly tested and functioning properly, this circuitry incurs a potentially high area overhead and performance penalty. This thesis focuses on using the existing BIST circuitry to test itself by utilizing a dedicated digital loopback path. A set of test procedures is developed and analyzed which
Worst Case Analysis of the Analog Circuits ELENA NICULESCU*, DORINAMIOARA PURCARU * and MARIUS
"... Abstract: An approach of the worst case analysis of the analog electronic circuits based on the circuit description in parameter space is proposed. A DC, AC or transient worstcase analysis can be performed only testing the circuit for the vertices of a polytope in conjunction with a circuit simula ..."
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Abstract: An approach of the worst case analysis of the analog electronic circuits based on the circuit description in parameter space is proposed. A DC, AC or transient worstcase analysis can be performed only testing the circuit for the vertices of a polytope in conjunction with a circuit simulator or computational environment. In order to validate and show the effectiveness of this approach, DC worstcase analyses of analog electronic circuits with symmetrical and asymmetrical tolerances in conjunction with a generalpurpose circuit simulator are presented and discussed. KeyWords: Tolerance, Analog electronic circuit, Worst case analysis. 1
A DECOMPOSITION METHOD FOR ANALOG FAULT LOCATION
"... In this paper, fault location in large analog networks by decomposition method is generalized to include subnetworks not explicitly testable. Assume that the network topology and nominal values of network components are known and the networkundertest is partitioned into subnetworks once for all. Th ..."
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In this paper, fault location in large analog networks by decomposition method is generalized to include subnetworks not explicitly testable. Assume that the network topology and nominal values of network components are known and the networkundertest is partitioned into subnetworks once for all. The decomposition nodes could be either the accessible nodes whose nodal voltages can be measured or the inaccessible nodes whose nodal voltages under faulty condition can be computed by a new method proposed in this paper. The new method reduces the test requirements for the number of accessible nodes and increases the flexibility of decomposition. Location of faulty subnetworks and subsequent location of faulty components are implemented based on checking consistency of the KCL equations for the decomposition nodes and using ambiguity group location techniques. This method can be applied to linear or nonlinear networks, and is particularly effective for the large scale analog networks. An example circuit is provided to illustrate the efficiency of the proposed method. 1.