Parametric faults are a significant cause of incorrect operation in analog circuits. Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration in which it is used. We present a design for test (DFT) scheme that offers the accuracy needed to test high-quality circuits. The DFT scheme is based on a circuit that digitally measures the ratio of a pair of capacitors. The circuit is used to characterize the transfer function of a switched capacitor circuit, which is usually determined by capacitor ratios. In our DFT scheme, capacitor ratios can be measured to within 0.01% accuracy and filter parameters can be shown to be satisfied to within 0.1% accuracy. With this characterization process, a filter can be directly shown to satisfy all specifications that depend on capacitor ratios. We believe the accuracy of our approach is at least an order of magnitude...

Current technology allows for the integration of complete systems onto a single chip. These systems on chip (SoC) are increasingly designed by connecting together large pre-designed and verified modules, called cores, with the advantage being a faster design cycle. The development of third party Intellectual Property (IP) cores is a rapidly expanding industry, and whereas initially these were nearly all digital, analogue IP cores are now representing a greater proportion of this market. In this report we consider issues which should be addressed when designing analogue IP cores, from low-level circuit realisations to high level design methodologies. The switched current (SI) technique can implement analogue functions on the most basic of digital processes and further advantages of high speed and low voltage operation, suggest that this may be particularly suitable for implementing analogue IP cores. In this work, we have considered the design of analogue SI filter cores, these being a fundamental analogue building block. The wave filter design technique has been found particularly suitable as a filter design method as it is easily implemented in SI and the

In analog circuits, process variations result in physical parameter variations. Simulated values must then be considered with there tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either '0' or '1' such that we can decide without ambiguity whether a fault is detectable or not, for analog circuits the fault detectability is a vague problem as the fault can either be completely detectable, partially detectable or completely undetectable which makes it very difficult to take a decision. In order to solve this decision problem, we have introduced the probability to detect fault (PDF) function which allows to formalize the problem of analog fault detection under parameter variations.

In analog integrated circuits, process variations result in physical parameter variations. Simulated performance values must then be considered with their tolerance intervals. Consequently, contrarily to digital circuits where the outputs are either '0' or '1' such that we can decide without ambiguity whether a fault is detectable or not, for analog circuits fault detectability is still a vague problem since the fault can either be completely detectable, partially detectable or completely undetectable which makes it very difficult to take a decision. In order to solve this decision problem, we have introduced the fault detection probability (FDP) function which allows to formalize the problem of analog fault detection subjected to parameter variations.