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Structuring and Automating Hardware Proofs in a HigherOrder TheoremProving Environment
 Formal Methods in System Design
, 1993
"... . In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically design ..."
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. In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically designed registertransfer circuits. By exploiting the structure of the underlying hardware proofs and limiting the form of descriptions used, we have attained nearly complete automation in proving the equivalences of the specifications and implementations. A hardwarespecific tool called MEPHISTO converts the original goal into a set of simpler subgoals, which are then automatically solved by a generalpurpose, firstorder prover called FAUST. Furthermore, the complete verification framework is being integrated within a commercial VLSI CAD framework. Keywords: hardware verification, higherorder logic 1 Introduction The past decade has witnessed the spiralling of interest within the academic com...
The TRuby Design System
, 1997
"... This paper describes the TRuby system for designing VLSI circuits, starting from formal specifications in which they are described in terms of relational abstractions of their behaviour. The design process involves correctnesspreserving transformations based on proved equivalences between relation ..."
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This paper describes the TRuby system for designing VLSI circuits, starting from formal specifications in which they are described in terms of relational abstractions of their behaviour. The design process involves correctnesspreserving transformations based on proved equivalences between relations, together with the addition of constraints. A class of implementable relations is defined. The tool enables such relations to be simulated or translated into a circuit description in VHDL. The design process is illustrated by the derivation of a circuit for 2dimensional convolution.
Formal Synthesis in Circuit Design  A Classification and Survey
, 1996
"... . This article gives a survey on different methods of formal synthesis. We define what we mean by the term formal synthesis and delimit it from the other formal methods that can also be used to guarantee the correctness of an implementation. A possible classification scheme for formal synthesis m ..."
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. This article gives a survey on different methods of formal synthesis. We define what we mean by the term formal synthesis and delimit it from the other formal methods that can also be used to guarantee the correctness of an implementation. A possible classification scheme for formal synthesis methods is then introduced, based on which some significant research activities are classified and summarized. We also briefly introduce our own approach towards the formal synthesis of hardware. Finally, we compare these approaches from different points of view. 1 Introduction In everyday use, synthesis means putting together of parts or elements so as to make up a complex whole. However in the circuit design domain, synthesis stands for a stepwise refinement of circuit descriptions from higher levels of abstraction (specifications) to lower ones (implementations), including optimizations within one abstraction level. Synthesis can be performed by hand for small circuits. Nowadays mor...
A Framework for Program Development Based on Schematic Proof
, 1993
"... Often, calculi for manipulating and reasoning about programs can be recast as calculi for synthesizing programs. The difference involves often only a slight shift of perspective: admitting metavariables into proofs. We propose that such calculi should be implemented in logical frameworks that suppor ..."
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Often, calculi for manipulating and reasoning about programs can be recast as calculi for synthesizing programs. The difference involves often only a slight shift of perspective: admitting metavariables into proofs. We propose that such calculi should be implemented in logical frameworks that support this kind of proof construction and that such an implementation can unify program verification and synthesis. Our proposal is illustrated with a worked example developed in Paulson's Isabelle system. We also give examples of existent calculi that are closely related to the methodology we are proposing and others that can be profitably recast using our approach.
A Transformational Approach to Formal Digital System Design
, 1993
"... syntax for design annotations : : : : : : : : : : : : : : : : : 45 4.3 Semantic algebras for design annotations : : : : : : : : : : : : : : : : 46 4.4 Semantic algebras, continued : : : : : : : : : : : : : : : : : : : : : : : 47 4.5 Valuation functions for design annotations : : : : : : : : : : : : ..."
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syntax for design annotations : : : : : : : : : : : : : : : : : 45 4.3 Semantic algebras for design annotations : : : : : : : : : : : : : : : : 46 4.4 Semantic algebras, continued : : : : : : : : : : : : : : : : : : : : : : : 47 4.5 Valuation functions for design annotations : : : : : : : : : : : : : : : 48 4.6 Devices : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 50 5.1 Constant dummy in the basic library : : : : : : : : : : : : : : : : : : 58 5.2 Interconnection devices in the basic library : : : : : : : : : : : : : : : 58 5.3 Devices in the comp library : : : : : : : : : : : : : : : : : : : : : : : 59 5.4 Timing analysis of the design in session box 7 : : : : : : : : : : : : : 66 5.5 Scheduling the design in session box 7 : : : : : : : : : : : : : : : : : : 67 5.6 The design after session box 8 : : : : : : : : : : : : : : : : : : : : : : 68 5.7 The design after session box 15 : : : : : : : : : : : : : : : : : : : : : 74 5.8 The design after session box 16 : : :...
A Practical Methodology for the Formal Verification of RISC Processors
, 1995
"... In this paper a practical methodology for formally verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters which reflects the abstraction levels used by a designer in the implementation of RISC cores, namely the architecture level, the pipeline stage leve ..."
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In this paper a practical methodology for formally verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters which reflects the abstraction levels used by a designer in the implementation of RISC cores, namely the architecture level, the pipeline stage level, the clock phase level and the hardware implementation. The use of this model allows us to successively prove the correctness between two neighbouring levels of abstractions, so that the verification process is simplified. The parallelism in the execution of the instructions, resulting from the pipelined architecture of RISCs is handled by splitting the proof into two independent steps. The first step shows that each architectural instruction is implemented correctly by the sequential execution of its pipeline stages. The second step shows that the instructions are correctly processed by the pipeline in that we prove that under certain constraints from the actual architecture, no conflic...
Implementation Issues about the Embedding of Existing High Level Synthesis Algorithms in HOL
, 1996
"... This article describes the embedding of high level synthesis algorithms in HOL. For given standard synthesis steps, we describe, how its data can be mapped to terms in HOL and the synthesis process be expressed by means of a logical derivation. In contrast to postsynthesis verification techniqu ..."
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This article describes the embedding of high level synthesis algorithms in HOL. For given standard synthesis steps, we describe, how its data can be mapped to terms in HOL and the synthesis process be expressed by means of a logical derivation. In contrast to postsynthesis verification techniques our approach is constructive in a sense that the proof is derived during synthesis rather than "guessed" afterwards. Therefore one does not get into the hardship of NPcompleteness or undecidability.
Modeling a Hardware Synthesis Methodology in Isabelle
 In Theorem Proving in Higher Order Logics (TPHOLs'96), volume 1125 of LNCS
, 1996
"... . Formal Synthesis is a methodology developed at Kent for combining circuit design and verification, where a circuit is constructed from a proof that it meets a given formal specification. We have reinterpreted this methodology in Isabelle's theory of higherorder logic so that circuits are incremen ..."
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. Formal Synthesis is a methodology developed at Kent for combining circuit design and verification, where a circuit is constructed from a proof that it meets a given formal specification. We have reinterpreted this methodology in Isabelle's theory of higherorder logic so that circuits are incrementally built during proofs using higherorder resolution. Our interpretation simplifies and extends Formal Synthesis both conceptually and in implementation. It also supports integration of this development style with other proofbased synthesis methodologies and leads to techniques for developing new classes of circuits, e.g., recursive descriptions of parametric designs. Keywords: Hardware verification and synthesis, theorem proving, higherorder logic, higherorder unification. 1. Introduction Verification by formal proof is time intensive and this is a burden in bringing formal methods into software and hardware design. One approach to reducing the verification burden is to combine develop...
Formally Embedding Existing High Level Synthesis Algorithms
 Correct Hardware Design and Verification Methods, number 987 in Lecture Notes in Computer Science
, 1995
"... This paper introduces a general scheme for formally embedding high level synthesis by formulating its basic steps as transformations within higher order logic. A functional representation of a data flow graph is successively refined by means of generic logical transformations. ..."
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This paper introduces a general scheme for formally embedding high level synthesis by formulating its basic steps as transformations within higher order logic. A functional representation of a data flow graph is successively refined by means of generic logical transformations.
Incremental Design and Formal Verification of Microcoded Microprocessors
 Theorem Provers in Circuit Design, Proceedings of the IFIP WG 10.2 International Working Conference
, 1992
"... A number of microprocessors have been specified and verified using machine supported formal techniques [2], [1], [7], [8], [10]. Some of these were preexisting designs, others were designed as part of the specification and verification project. Even in the case of new designs, the formal techniques ..."
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A number of microprocessors have been specified and verified using machine supported formal techniques [2], [1], [7], [8], [10]. Some of these were preexisting designs, others were designed as part of the specification and verification project. Even in the case of new designs, the formal techniques used offered very little support for incremental design and verification. Support for incremental design and verification means that certain additions to the implementation and/or specification can be verified without reverification of the previous parts. Here, we present techniques for incremental design and verification which, as well as providing more appropriate models, also make the formal verification more efficient. The formal framework to support these ideas has been implemented in the HOL system and has been used in the specification, design and verification of a microcoded microprocessor. The techniques deal with three different aspects of the microprocessor: specification of mac...