Transient Signal Analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points. The power supply transient signals of an 8-bit multiplier are analyzed using both hardware and simulations experiments. The small signal variations generated at these test points are analyzed in both the time and frequency domain. A simple statistical procedure is presented that captures the variation introduced by defects while attenuating those variations introduced by process variations. The results of the analysis show that it is possible to distinguish between defect-free and defective devices in both simulations and hardware. Transient Signal Analysis (TSA) is a parametric

A delay-fault testing strategy based on the analysis of power supply transient signals is presented. The method is an extension to a Go/No-Go device testing method called Transient Signal Analysis (TSA) [1]. TSA detects defects through the analysis of a set of power supply transient waveforms in the time or frequency domain, e.g., Fourier phase components. A recent extension to TSA demonstrated a correlation between the V DDT Fourier phase components and path delays in defect-free devices [2]. The method proposed here is able to detect increases in delay due to resistive shorting and open defects using a similar technique. In particular, simulation results show that a delay defective device can be distinguished from a defect-free device through an anomaly in the Fourier phase

Dynamic supply current (IDD) analysis has emerged as an e ective way for defect oriented testing of analog circuits. In this paper,wepropose using wavelet decomposition of IDD for fault detection in analog circuits. Wavelet transform has the property of resolving events in both time and frequency domain simultaneously unlike fourier expansion which localizes a signal in terms of frequency only. Wavelet transform also has better sub-banding property than fourier and it can be easily adapted to current waveforms from di erent circuits. These make wavelet a more suitable candidate for fault detection in analog circuits than pure time-domain or pure frequency-domain methods. We have shown that for equivalent number of spectral components, sensitivity of wavelet based fault detection is much higher than fourier or time-domain analysis for both catastrophic and parametric faults. Experimental results on benchmark circuits show that wavelet based method ison average 25 times more sensitive than DFT for parametric faults and can be considered asapromising alternative for analog fault detection amidst measurement hardware noise and process variation. I.

Defect Simulation Model for i DDT Testing

This paper presents an iDDT test method for embedded CMOS SRAMs. A total of 219 faults were inserted and simulated using parameters from a 0.5 um bulk CMOS process. The SRAM model includes realistic effects such as wire bonding inductance and resistance parameters as well as bypass capacitances. An iDDT sensor is introduced and incorporated into the SRAM cell array to detect abnormal iDDT switching.