Results 1  10
of
16
Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
Abstract

Cited by 103 (32 self)
 Add to MetaCart
This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
Checkpointing and its applications
 IEEE, IEEE Computer Society
, 1995
"... Is the Framingham coronary heart disease absolute risk function ..."
Abstract

Cited by 84 (8 self)
 Add to MetaCart
Is the Framingham coronary heart disease absolute risk function
Optimal Wire and Transistor Sizing for Circuits with NonTree Topology
 in Proc. Int. Conf. on Computer Aided Design
, 1997
"... Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree ..."
Abstract

Cited by 28 (11 self)
 Add to MetaCart
Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of significant importance to highperformance deep submicron design including, for example, circuits with loops of resistors, e.g., clock distribution meshes, and circuits with coupling capacitors, e.g., buses with crosstalk between the lines. The paper proposes a new optimization method which can be used to address these problems. The method uses the dominant time constant as a measure of signal propagation delay in an RC circuit, instead of Elmore delay. Using this measure, sizing of any RC circuit can be cast as a convex optimization problem which can be solved using the recently developed efficient interi...
An Efficient Approach To Simultaneous Transistor And Interconnect Sizing
 IN PROC. INT. CONF. ON COMPUTER AIDED DESIGN
, 1996
"... In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We define a class of optimization problems as CHposynomial programs and reveal a general dominance property for all CHposynomial programs (Theorem 1). We show that the STIS problems under a number of transi ..."
Abstract

Cited by 16 (8 self)
 Add to MetaCart
In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We define a class of optimization problems as CHposynomial programs and reveal a general dominance property for all CHposynomial programs (Theorem 1). We show that the STIS problems under a number of transistor delay models are CHposynomial programs and propose an efficient and nearoptimal STIS algorithm based on the dominance property. When used to solve the simultaneous driver/buffer and wire sizing problem for real designs, it reduces the maximum delay by up to 17.7%, and more significantly, reduces the power consumption by a factor of 61.6%, when compared with the original designs. When used to solve the transistor sizing problem, it achieves a smooth areadelay tradeoff. Moreover, the algorithm optimizes a clock net of 367 drivers/buffers and 59304mlong wire in 120 seconds, and a 32bit adder with 1,026 transistors in 66 seconds on a SPARC5 workstation.
Optimizing dominant time constant in RC circuits
, 1996
"... We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interestin ..."
Abstract

Cited by 16 (8 self)
 Add to MetaCart
We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interesting design problems as convex optimization problems, specifically, semidefinite programs (SDPs). For example, assuming that the conductances and capacitances are affine functions of the design parameters (which is a common model in transistor or interconnect wire sizing), one can minimize the power consumption or the area subject to an upper bound on the dominant time constant, or compute the optimal tradeoff surface between power, dominant time constant, and area. We will also note that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires. This approach has two advantages over methods based on Elmore delay optimization. First, it handles a far wider class of circuits, e.g., those with nongrounded capacitors. Second, it always results in convex optimization problems for which very efficient interiorpoint methods have recently been developed. We illustrate the method, and extensions, with several examples involving optimal wire and transistor sizing.
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area
 PROC. ICCAD
, 1993
"... This paper examines the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification under the standardcell paradigm. This is effected by appropriately selecting a size for each gate in the circuit from a standardcell library, and by adjusting the delay ..."
Abstract

Cited by 8 (0 self)
 Add to MetaCart
This paper examines the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification under the standardcell paradigm. This is effected by appropriately selecting a size for each gate in the circuit from a standardcell library, and by adjusting the delays between the central clock distribution node and individual ipflops. Traditional methods treat these two problems separately, which may lead to very suboptimal solutions in some cases. Experimental results show that by considering the two problems together, it is not only possible to reduce the optimized circuit area, but also to achieve faster clocking frequencies. We also address the problem of making this work applicable to very large synchronous sequential circuits by partitioning these circuits to reduce the computational complexity.
An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs
 in Proc. Int. Symp. on Physical Design
, 1997
"... In this paper, we formulated a new class of optimization problem, named the general CHposynomial program, which is more general than the simple and boundedvariation CHposynomial programs in [1]. We revealed the general dominance property so that an efficient and unified algorithm based on the loc ..."
Abstract

Cited by 7 (2 self)
 Add to MetaCart
In this paper, we formulated a new class of optimization problem, named the general CHposynomial program, which is more general than the simple and boundedvariation CHposynomial programs in [1]. We revealed the general dominance property so that an efficient and unified algorithm based on the local refinement (LR) operation can be used to optimize the simple, boundedvariation and general CHposynomial programs. We applied the LRbased optimization algorithm to solve the device sizing problem using accurate tablebased model, and the wire sizing and spacing problem with consideration of coupling between multiple nets. Both problems are solved in the context of simultaneous device and wire sizing optimization for deep submicron designs. Experiments show that our LRbased optimization algorithm is very effective and extremely efficient. Up to 16.5% delay reduction is observed when compared with previous work based on the simple device model [1], and up to 31% delay reduction and 100x speedup is observed when compared the global interconnect sizing and spacing work [2]. We believe that our general CHposynomial formulation and LRbased algorithm can also be applied to other optimization problems in the CAD field.
Revisiting the Linear Programming Framework for Leakage Power vs. Performance Optimization
 Proc. Proc. of International Symposium on Quality Electronic Design, 2009
"... Abstract — This paper revisits and extends a general linear programming (LP) formulation to exploit multiple knobs such as multiLgate footprintcompatible libraries and postlayout Lgatebiasing to minimize total leakage power under timing constraints. We minimize positive timing slack for each cell ..."
Abstract

Cited by 7 (6 self)
 Add to MetaCart
Abstract — This paper revisits and extends a general linear programming (LP) formulation to exploit multiple knobs such as multiLgate footprintcompatible libraries and postlayout Lgatebiasing to minimize total leakage power under timing constraints. We minimize positive timing slack for each cell according to its leakage vs. delay sensitivity, so that unnecessary leakage power consumption is saved without degrading circuit performance. A key difference between our work and previous works is that we preprocess timing libraries to estimate the linear relation – in every slewload condition – between the gate delay and gate length by linear fitting; we then optimize total leakage power by estimating the optimal gate length for each gate using fast linear programming. With a 65GP industry testbed, and directly comparing with commercial tools, we show the QOR and runtime advantages of our method for the multiLgate and Lgatebiasing knobs. We also show a promising application to circuit timing legalization, a problem which frequently arises when implementation and signoff timers differ. Overall, our results show strong viability of LP based estimation and optimization: compared with the commercial tools, we: (1) shift the achievable delayleakage tradeoff curve in a positive way, and (2) more accurately maintain prescribed timing constraints.
Simultaneous Transistor and Interconnect Sizing Using General Dominance Property
 in Proc. ACM SIGDA Workshop on Physical Design
, 1995
"... In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. Our contributions include: (1) We formulated the STIS problem using a distributed RC circuit model which models the waveformdependent transistor resistances, the distributed nature of the interconnects and th ..."
Abstract

Cited by 6 (5 self)
 Add to MetaCart
In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. Our contributions include: (1) We formulated the STIS problem using a distributed RC circuit model which models the waveformdependent transistor resistances, the distributed nature of the interconnects and the transistorinterconnect interactions. (2) We showed a general dominance property for a large class of posynomial functions (Theorems 1 and 2) and developed efficient algorithms based on recursive local refinement or bundled refinement for optimizing such functions. Although our intended application is to develop optimal algorithms for the STIS problem under a wide range of transistor and interconnect models, it also has direct applications to many other optimization problems in VLSI CAD and other domains. (3) Based on the general dominance property, we developed efficient and optimal algorithms for the STIS problem, which are much more efficient than the mathematical programming based methods such as the convexprogramming based transistorsizing and superior to the sensitivitybased heuristics used in many transistor or interconnect sizing works in terms of both global convergence and optimality. The preliminary experiments for both transistor sizing and simultaneous transistor and interconnect sizing are reported. To our knowledge, this is the first indepth study of the simultaneous transistor and interconnect sizing problem. 1 1
Modeling and Optimization of VLSI Interconnects
, 1999
"... As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimizati ..."
Abstract

Cited by 5 (0 self)
 Add to MetaCart
As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimization, and interconnect extraction and modeling: the multisource wire sizing (MSWS) problem, the simultaneous transistor and interconnect sizing (STIS) problem, the global interconnect sizing and spacing (GISS) problem, the interconnect capacitance extraction problem, and the interconnect inductance extraction problems. Given a routing tree with multiple sources, the MSWS problem determines the optimal widths of the wire segments such that the delay is minimized. We reveal several interesting properties for the optimal MSWS solution, of which the most important is the bundled refinement property. Based on this property, we propose a polynomial time algorithm, which uses iterative bundled refinement operations to compute lower and upper bounds of an optimal solution. Since the algorithm often achieves identical lower and upper bounds in experiments, the optimal solution is obtained simply by the bound computation. Furthermore, this algorithm can be used for singlesource wire sizing problem and runs 100x xxi faster than previous methods. It has replaced previous singlesource wire sizing methods in practice.