This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, non-tree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.

In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We define a class of optimization problems as CH-posynomial programs and reveal a general dominance property for all CH-posynomial programs (Theorem 1). We show that the STIS problems under a number of transistor delay models are CH-posynomial programs and propose an efficient and near-optimal STIS algorithm based on the dominance property. When used to solve the simultaneous driver/buffer and wire sizing problem for real designs, it reduces the maximum delay by up to 17.7%, and more significantly, reduces the power consumption by a factor of 61.6%, when compared with the original designs. When used to solve the transistor sizing problem, it achieves a smooth area-delay trade-off. Moreover, the algorithm optimizes a clock net of 367 drivers/buffers and 59304m-long wire in 120 seconds, and a 32bit adder with 1,026 transistors in 66 seconds on a SPARC-5 workstation.

Abstract — We propose a transistor sizing method that downsizes MOSFETs inside a cell to eliminate redundancy of cell-based circuits as much as possible. Our method reduces power dissipation of detail-routed circuits while preserving interconnects. The effectiveness of our method is experimentally evaluated using 5 circuits. The power dissipation is reduced by 77 % maximum and 65 % on average without delay increase. I.

In this paper, we formulated a new class of optimization problem, named the general CH-posynomial program, which is more general than the simple and bounded-variation CH-posynomial programs in [1]. We revealed the general dominance property so that an efficient and unified algorithm based on the local refinement (LR) operation can be used to optimize the simple, bounded-variation and general CH-posynomial programs. We applied the LR-based optimization algorithm to solve the device sizing problem using accurate table-based model, and the wire sizing and spacing problem with consideration of coupling between multiple nets. Both problems are solved in the context of simultaneous device and wire sizing optimization for deep submicron designs. Experiments show that our LR-based optimization algorithm is very effective and extremely efficient. Up to 16.5% delay reduction is observed when compared with previous work based on the simple device model [1], and up to 31% delay reduction and 100x speedup is observed when compared the global interconnect sizing and spacing work [2]. We believe that our general CH-posynomial formulation and LR-based algorithm can also be applied to other optimization problems in the CAD field.

As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimization, and interconnect extraction and modeling: the multi-source wire sizing (MSWS) problem, the simultaneous transistor and interconnect sizing (STIS) problem, the global interconnect sizing and spacing (GISS) problem, the interconnect capacitance extraction problem, and the interconnect inductance extraction problems. Given a routing tree with multiple sources, the MSWS problem determines the optimal widths of the wire segments such that the delay is minimized. We reveal several interesting properties for the optimal MSWS solution, of which the most important is the bundled refinement property. Based on this property, we propose a polynomial time algorithm, which uses iterative bundled refinement operations to compute lower and upper bounds of an optimal solution. Since the algorithm often achieves identical lower and upper bounds in experiments, the optimal solution is obtained simply by the bound computation. Furthermore, this algorithm can be used for single-source wire sizing problem and runs 100x xxi faster than previous methods. It has replaced previous single-source wire sizing methods in practice.

Gate sizing is used to scale the drive capability of CMOS-gates in order to improve the timing or to reduce the power dissipation of a logic circuit. Gate sizing can be formulated as a nonlinear optimization problem. This nonlinear optimization problem in turn can be linearized. The resulting linear programming formulation can be solved by an interior point method. Solving this linear program takes considerable time and the accuracy typically required for gate sizing is not too demanding. A possibility for a speed-accuracy trade-off exists. We propose to use the primal-dual gap of an interior point method for linear programming as a measure of not only the achieved accuracy of the objective function, but also as a measure of the achieved accuracy of the sizing factors of individual gates. Terminating early once the desired accuracy is reached renders runtime improvements. Keywords--- logic synthesis, timing and power optimization, interior point methods I. Introduction Gate sizing i...

Gate sizing is used to increase the performance and/or decrease the area and/or power dissipation of CMOS circuits. There has been extensive work on gate sizing introducing several different methods, producing mixed results in solving speed, size of benchmark circuits and accuracy. These papers however rarely make comparisons between solving methods and usually only use small benchmarks. We introduce a sizable model for CMOS gates. Using this model we describe a gate sizing formulation for CMOS circuits. This model contains linear and some nonlinear equations. We solve the gate sizing formulation with three linear programming solvers for which we linearize the nonlinear equations. We also solve the gate sizing problem with a geometric and a general nonlinear programming solver. We present results for the five solvers for circuits up to a several thousand gates. We also discuss the advantages and disadvantages of each solver for the purpose of gate sizing.