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Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
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Cited by 115 (32 self)
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This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
An Efficient Approach To Simultaneous Transistor And Interconnect Sizing
 IN PROC. INT. CONF. ON COMPUTER AIDED DESIGN
, 1996
"... In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We define a class of optimization problems as CHposynomial programs and reveal a general dominance property for all CHposynomial programs (Theorem 1). We show that the STIS problems under a number of transi ..."
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Cited by 16 (8 self)
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In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We define a class of optimization problems as CHposynomial programs and reveal a general dominance property for all CHposynomial programs (Theorem 1). We show that the STIS problems under a number of transistor delay models are CHposynomial programs and propose an efficient and nearoptimal STIS algorithm based on the dominance property. When used to solve the simultaneous driver/buffer and wire sizing problem for real designs, it reduces the maximum delay by up to 17.7%, and more significantly, reduces the power consumption by a factor of 61.6%, when compared with the original designs. When used to solve the transistor sizing problem, it achieves a smooth areadelay tradeoff. Moreover, the algorithm optimizes a clock net of 367 drivers/buffers and 59304mlong wire in 120 seconds, and a 32bit adder with 1,026 transistors in 66 seconds on a SPARC5 workstation.
PostLayout Transistor Sizing for Power Reduction
 Proc. of ACM/IEEE Design Automation Conference. (ASPDAC
, 2001
"... Abstract — We propose a transistor sizing method that downsizes MOSFETs inside a cell to eliminate redundancy of cellbased circuits as much as possible. Our method reduces power dissipation of detailrouted circuits while preserving interconnects. The effectiveness of our method is experimentally e ..."
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Cited by 14 (4 self)
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Abstract — We propose a transistor sizing method that downsizes MOSFETs inside a cell to eliminate redundancy of cellbased circuits as much as possible. Our method reduces power dissipation of detailrouted circuits while preserving interconnects. The effectiveness of our method is experimentally evaluated using 5 circuits. The power dissipation is reduced by 77 % maximum and 65 % on average without delay increase. I.
An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs
 in Proc. Int. Symp. on Physical Design
, 1997
"... In this paper, we formulated a new class of optimization problem, named the general CHposynomial program, which is more general than the simple and boundedvariation CHposynomial programs in [1]. We revealed the general dominance property so that an efficient and unified algorithm based on the loc ..."
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Cited by 7 (2 self)
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In this paper, we formulated a new class of optimization problem, named the general CHposynomial program, which is more general than the simple and boundedvariation CHposynomial programs in [1]. We revealed the general dominance property so that an efficient and unified algorithm based on the local refinement (LR) operation can be used to optimize the simple, boundedvariation and general CHposynomial programs. We applied the LRbased optimization algorithm to solve the device sizing problem using accurate tablebased model, and the wire sizing and spacing problem with consideration of coupling between multiple nets. Both problems are solved in the context of simultaneous device and wire sizing optimization for deep submicron designs. Experiments show that our LRbased optimization algorithm is very effective and extremely efficient. Up to 16.5% delay reduction is observed when compared with previous work based on the simple device model [1], and up to 31% delay reduction and 100x speedup is observed when compared the global interconnect sizing and spacing work [2]. We believe that our general CHposynomial formulation and LRbased algorithm can also be applied to other optimization problems in the CAD field.
Modeling and Optimization of VLSI Interconnects
, 1999
"... As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimizati ..."
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Cited by 6 (0 self)
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As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimization, and interconnect extraction and modeling: the multisource wire sizing (MSWS) problem, the simultaneous transistor and interconnect sizing (STIS) problem, the global interconnect sizing and spacing (GISS) problem, the interconnect capacitance extraction problem, and the interconnect inductance extraction problems. Given a routing tree with multiple sources, the MSWS problem determines the optimal widths of the wire segments such that the delay is minimized. We reveal several interesting properties for the optimal MSWS solution, of which the most important is the bundled refinement property. Based on this property, we propose a polynomial time algorithm, which uses iterative bundled refinement operations to compute lower and upper bounds of an optimal solution. Since the algorithm often achieves identical lower and upper bounds in experiments, the optimal solution is obtained simply by the bound computation. Furthermore, this algorithm can be used for singlesource wire sizing problem and runs 100x xxi faster than previous methods. It has replaced previous singlesource wire sizing methods in practice.
Total Power Optimization Combining Placement, Sizing and
 MultiVth Through Slack Distribution Management, Proc. IEEE/ACM Asia and South Pacic Design Automation Conf
"... Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power and timing are often conflicting objectives during optimization. In this paper, we propose a novel total power optimizati ..."
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Cited by 2 (0 self)
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Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power and timing are often conflicting objectives during optimization. In this paper, we propose a novel total power optimization flow under performance constraint. Instead of using placement, gate sizing, and multipleVt assignment techniques independently, we combine them together through the concept of slack distribution management to maximize the potential for power reduction. We propose to use the linear programming (LP) based placement and the geometric programming (GP) based gate sizing formulations to improve the slack distribution, which helps to maximize the total power reduction during the Vtassignment stage. Our formulations include important practical design constraints, such as slew, noise and short circuit power, which were often ignored previously. We tested our algorithm on a set of industrialstrength manually optimized circuits from a multiGHz 65nm microprocessor, and obtained very promising results. To our best knowledge, this is the first work that combines placement, gate sizing and Vt swapping systematically for total power (and in particular leakage) management. 1.
Comparison of Gate Sizing Formulations and Solving Methods
"... Gate sizing is used to increase the performance and/or decrease the area and/or power dissipation of CMOS circuits. There has been extensive work on gate sizing introducing several different methods, producing mixed results in solving speed, size of benchmark circuits and accuracy. These papers howe ..."
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Gate sizing is used to increase the performance and/or decrease the area and/or power dissipation of CMOS circuits. There has been extensive work on gate sizing introducing several different methods, producing mixed results in solving speed, size of benchmark circuits and accuracy. These papers however rarely make comparisons between solving methods and usually only use small benchmarks. We introduce a sizable model for CMOS gates. Using this model we describe a gate sizing formulation for CMOS circuits. This model contains linear and some nonlinear equations. We solve the gate sizing formulation with three linear programming solvers for which we linearize the nonlinear equations. We also solve the gate sizing problem with a geometric and a general nonlinear programming solver. We present results for the five solvers for circuits up to a several thousand gates. We also discuss the advantages and disadvantages of each solver for the purpose of gate sizing.
SpeedAccuracy Tradeoff in Gate Sizing
"... Gate sizing is used to scale the drive capability of CMOSgates in order to improve the timing or to reduce the power dissipation of a logic circuit. Gate sizing can be formulated as a nonlinear optimization problem. This nonlinear optimization problem in turn can be linearized. The resulting linear ..."
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Gate sizing is used to scale the drive capability of CMOSgates in order to improve the timing or to reduce the power dissipation of a logic circuit. Gate sizing can be formulated as a nonlinear optimization problem. This nonlinear optimization problem in turn can be linearized. The resulting linear programming formulation can be solved by an interior point method. Solving this linear program takes considerable time and the accuracy typically required for gate sizing is not too demanding. A possibility for a speedaccuracy tradeoff exists. We propose to use the primaldual gap of an interior point method for linear programming as a measure of not only the achieved accuracy of the objective function, but also as a measure of the achieved accuracy of the sizing factors of individual gates. Terminating early once the desired accuracy is reached renders runtime improvements. Keywords logic synthesis, timing and power optimization, interior point methods I. Introduction Gate sizing i...