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17
Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
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Cited by 115 (32 self)
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This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
Gate Sizing for Constrained delay/power/area optimization
 in IEEE Transcation on VLSI Design
, 1997
"... Abstract—Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to mini ..."
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Cited by 38 (1 self)
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Abstract—Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to minimize the power consumption and/or the area of a circuit under some userdefined delay constraints, or to obtain the fastest circuit within a given power budget. Although this technologydependent optimization has been investigated for years, the proposed approaches sometimes rely on assumptions, cost models, or algorithms that make them unrealistic or impossible to apply on reallife large circuits. We discusse here a gate sizing algorithm (GS), and show how it is used to achieve constrained optimization. It can be applied on large circuits within a reasonable CPU time, e.g., minimizing the power of a 10000 nodes circuit under some delay constraint in 2 hours. Keywords—Gate sizing, discrete constrained optimization, delay/power/area tradeoff I.
New Algorithms for Gate Sizing: A Comparative Study
 IN DAC
, 1996
"... Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing alg ..."
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Cited by 34 (1 self)
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Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing algorithms targeting discrete, nonlinear, nonunimodal, constrained optimization. The goal is to overcome the nonlinearity and nonunimodality of the delay and the power to achieve good quality results within a reasonable CPU time, e.g., handling a 10000 node network in 2 hours. We compare the five algorithms on constraint free delay optimization and delay constrained power optimization, and show that one method is superior to the others.
Gate Sizing: a General Purpose Optimization Approach
, 1996
"... Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. The methods previously proposed to address this problem suffer from problems that makes them difficult to apply on reallife large c ..."
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Cited by 17 (2 self)
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Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. The methods previously proposed to address this problem suffer from problems that makes them difficult to apply on reallife large circuits. This paper presents the gate sizing algorithm GS, which has the following characteristics. It is a general purpose optimizer, e.g., it can optimize the power or/and area under some delay constraints, or the delay under some power or/and area constraints. It is oriented to a pure combinatorial optimization, and addresses nonlinear, nonunimodal, constrained optimization, which enables it to handle complex cost models. It can take into account user defined or library dependent design rules. It can be applied on large circuits within a reasonable CPU time, e.g., 10000 nodes in 2 hours.
An Efficient Approach To Simultaneous Transistor And Interconnect Sizing
 IN PROC. INT. CONF. ON COMPUTER AIDED DESIGN
, 1996
"... In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We define a class of optimization problems as CHposynomial programs and reveal a general dominance property for all CHposynomial programs (Theorem 1). We show that the STIS problems under a number of transi ..."
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Cited by 16 (8 self)
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In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We define a class of optimization problems as CHposynomial programs and reveal a general dominance property for all CHposynomial programs (Theorem 1). We show that the STIS problems under a number of transistor delay models are CHposynomial programs and propose an efficient and nearoptimal STIS algorithm based on the dominance property. When used to solve the simultaneous driver/buffer and wire sizing problem for real designs, it reduces the maximum delay by up to 17.7%, and more significantly, reduces the power consumption by a factor of 61.6%, when compared with the original designs. When used to solve the transistor sizing problem, it achieves a smooth areadelay tradeoff. Moreover, the algorithm optimizes a clock net of 367 drivers/buffers and 59304mlong wire in 120 seconds, and a 32bit adder with 1,026 transistors in 66 seconds on a SPARC5 workstation.
Simultaneous Gate Sizing and Placement
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2000
"... In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and op ..."
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Cited by 13 (3 self)
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In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. More precisely in each iteration, we perform three operations: a) reposition the immediate fanouts of the gates on the kmost critical paths; b) size down the immediate fanouts of the gates on the kmost critical paths; c) simultaneously reposition and resize the gates on the kmost critical paths. Each of these operations is formulated and solved as a mathematical program by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches which separate gate sizing from gate placement. 1
Simultaneous gate sizing and fanout optimization
 In Proceedings IEEEACM International Conference on ComputerAided Design
, 2000
"... This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timingcritical paths in a circuit. First, a continuousvariable delay model that captures both sizing and buffering effects is presented. Next, the optimization problem is formulated as a nonconvex mat ..."
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Cited by 6 (1 self)
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This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timingcritical paths in a circuit. First, a continuousvariable delay model that captures both sizing and buffering effects is presented. Next, the optimization problem is formulated as a nonconvex mathematical program. To manage the problem size, only a small number of critical paths are considered simultaneously. The mathematical program is solved by a nonlinear programming package. Finally, a design flow based on iterative selection and optimization of the k most critical paths in the circuit is proposed. Experimental results show that the proposed flow reduces the circuit delay by an average of 9.2 % compared to conventional flows that separate gate sizing from fanout optimization. 1
Computing the Entire Active Area / Power Consumption versus Delay Tradeoff Curve for Gate Sizing with a Piecewise Linear Simulator
, 1994
"... The gate sizing problem is the problem of finding load drive capabilities for all gates in a given Boolean network such, that a given delay limit is kept, and the necessary cost in terms of active area usage and / or power consumption is minimal. This paper describes a way to obtain the entire cost ..."
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Cited by 5 (3 self)
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The gate sizing problem is the problem of finding load drive capabilities for all gates in a given Boolean network such, that a given delay limit is kept, and the necessary cost in terms of active area usage and / or power consumption is minimal. This paper describes a way to obtain the entire cost versus delay tradeoff curve of a combinational logic circuit in an efficient way. Every point on the resulting curve is the global optimum of the corresponding gate sizing problem. The problem is solved by mapping it onto piecewise linear models in such a way, that a piecewise linear (circuit) simulator can do the job. It is shown that this setup is very efficient, and can produce tradeoff curves for large circuits (thousands of gates) in a few minutes. Benchmark results for the entire set of MCNC '91 twolevel examples are given. Keywords Logic Synthesis, Gate Sizing, Transistor Sizing, Low Power, Linear Programming, Circuit Simulation I. Introduction A. The gate sizing problem The ...
A power optimization method considering glitch reduction by gate sizing
 Proc. ISLPED
, 1998
"... We propose a power optimization method considering glitch reduction by gate sizing. Our method reduces not only the amount of capacitive and shortcircuit power consumption but also the power dissipated by glitches which has not been exploited previously. In the optimization method, we improve the ..."
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Cited by 5 (1 self)
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We propose a power optimization method considering glitch reduction by gate sizing. Our method reduces not only the amount of capacitive and shortcircuit power consumption but also the power dissipated by glitches which has not been exploited previously. In the optimization method, we improve the accuracy of statistical glitch estimation method and device a gate sizing algorithm that utilizes perturbations for escaping a bad local solution. The effect of our method is verified experimentally using 12 benchmark circuits with a 0.5 m standard cell library. Gate sizing reduces the number of glitch transitions by 38.2 % on average and by 63.4 % maximum. This results in the reduction of total transitions by 12.8 % on average. When the circuits are optimized for power without delay constraints, the power dissipation is reduced by 7.4 % on average and by 15.7 % maximum further from the minimumsized circuits. 1
M.Pedram “Gate sizing with controlled Displacement
 in Proceedings of international symposium on physical design
"... Abstract In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively ident ..."
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Cited by 2 (1 self)
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Abstract In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. All the operations are formulated and solved as mathematical programming problems by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches, which separate gate sizing from gate placement. 1