This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, non-tree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.

Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing algorithms targeting discrete, non-linear, non-unimodal, constrained optimization. The goal is to overcome the non-linearity and nonunimodality of the delay and the power to achieve good quality results within a reasonable CPU time, e.g., handling a 10000 node network in 2 hours. We compare the five algorithms on constraint free delay optimization and delay constrained power optimization, and show that one method is superior to the others. 1 Introduction Early work on gate sizing targeting area/delay optimization can be found in [20, 12]. Using a RC delay model, TILOS [8] expresses the delay and area as posynomials. Geometric programming or heuristics based greedy approaches can be used to so...

In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We define a class of optimization problems as CH-posynomial programs and reveal a general dominance property for all CH-posynomial programs (Theorem 1). We show that the STIS problems under a number of transistor delay models are CH-posynomial programs and propose an efficient and near-optimal STIS algorithm based on the dominance property. When used to solve the simultaneous driver/buffer and wire sizing problem for real designs, it reduces the maximum delay by up to 17.7%, and more significantly, reduces the power consumption by a factor of 61.6%, when compared with the original designs. When used to solve the transistor sizing problem, it achieves a smooth area-delay trade-off. Moreover, the algorithm optimizes a clock net of 367 drivers/buffers and 59304m-long wire in 120 seconds, and a 32bit adder with 1,026 transistors in 66 seconds on a SPARC-5 workstation.

Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. The methods previously proposed to address this problem suffer from problems that makes them difficult to apply on real-life large circuits. This paper presents the gate sizing algorithm GS, which has the following characteristics. It is a general purpose optimizer, e.g., it can optimize the power or/and area under some delay constraints, or the delay under some power or/and area constraints. It is oriented to a pure combinatorial optimization, and addresses non-linear, non-unimodal, constrained optimization, which enables it to handle complex cost models. It can take into account user defined or library dependent design rules. It can be applied on large circuits within a reasonable CPU time, e.g., 10000 nodes in 2 hours.

In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. More precisely in each iteration, we perform three operations: a) reposition the immediate fan-outs of the gates on the k-most critical paths; b) size down the immediate fan-outs of the gates on the k-most critical paths; c) simultaneously reposition and resize the gates on the k-most critical paths. Each of these operations is formulated and solved as a mathematical program by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches which separate gate sizing from gate placement. 1

The gate sizing problem is the problem of finding load drive capabilities for all gates in a given Boolean network such, that a given delay limit is kept, and the necessary cost in terms of active area usage and / or power consumption is minimal. This paper describes a way to obtain the entire cost versus delay trade-off curve of a combinational logic circuit in an efficient way. Every point on the resulting curve is the global optimum of the corresponding gate sizing problem. The problem is solved by mapping it onto piecewise linear models in such a way, that a piecewise linear (circuit) simulator can do the job. It is shown that this setup is very efficient, and can produce trade-off curves for large circuits (thousands of gates) in a few minutes. Benchmark results for the entire set of MCNC '91 two-level examples are given. Keywords--- Logic Synthesis, Gate Sizing, Transistor Sizing, Low Power, Linear Programming, Circuit Simulation I. Introduction A. The gate sizing problem The ...

In this paper � we study the simultaneous transistor and in� terconnect sizing �STIS � problem. We de�ne a class of opti� mization problems as CH�posynomial programs and reveal a general dominance property for all CH�posynomial pro� grams �Theorem 1�. We show that the STIS problems un� der a number of transistor delay models are CH�posynomial programs and propose an e�cient and near�optimal STIS algorithm based on the dominance property. When used to solve the simultaneous driver�bu�er and wire sizing prob� lem for real designs � it reduces the maximum delay byupto 16.1� � and more signi�cantly � reduces the power consump� tion by a factor of 1.63x � when compared with the original designs. When used to solve the transistor sizing problem� it achieves a smooth area�delay trade�o�. Moreover � the algorithm optimizes a clock net of 367 drivers�bu�ers and 59304�m�long wire in 120 seconds � and a 32bit adder with 1�026 transistors in 66 seconds on a SPARC�5 workstation. 1.

Introduction Generation of mask layout for static CMOS cells from a boolean specification has been done for many years now, especially in research environments. However in commercial systems standard cell libraries providing a limited choice of cells are most popular. With logic synthesis widely available in commercial systems now, a cell generator can show remarkable advantages. This requires particular attention for cell timing behavior and routing transparency, in combination with a consistent timing model in the logic synthesis package. As result high performance circuits can be generated, with a reduced cell count and fast and reliable timing. 2. Static CMOS cell style Static CMOS cells have a general circuit topology as depicted in figure 1. Such a function is normally specified as the inverse of a nested expression built from input identifiers, and symbols, or symbols, and braces. The internal structure of the N-- and P-

This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that captures both sizing and buffering effects is presented. Next, the optimization problem is formulated as a non-convex mathematical program. To manage the problem size, only a small number of critical paths are considered simultaneously. The mathematical program is solved by a non-linear programming package. Finally, a design flow based on iterative selection and optimization of the k most critical paths in the circuit is proposed. Experimental results show that the proposed flow reduces the circuit delay by an average of 10% compared to conventional flows that separate gate sizing from fanout optimization.

Gate sizing is used to increase the performance and/or decrease the area and/or power dissipation of CMOS circuits. There has been extensive work on gate sizing introducing several different methods, producing mixed results in solving speed, size of benchmark circuits and accuracy. These papers however rarely make comparisons between solving methods and usually only use small benchmarks. We introduce a sizable model for CMOS gates. Using this model we describe a gate sizing formulation for CMOS circuits. This model contains linear and some nonlinear equations. We solve the gate sizing formulation with three linear programming solvers for which we linearize the nonlinear equations. We also solve the gate sizing problem with a geometric and a general nonlinear programming solver. We present results for the five solvers for circuits up to a several thousand gates. We also discuss the advantages and disadvantages of each solver for the purpose of gate sizing.