The traditional way of approaching placement problems in computer-aided design (CAD) tools for analog layout is to explore an extremely large search space of feasible or unfeasible placement configurations, where the cells are moved in the chip plane (being even allowed to overlap in possibly illegal ways) by a stochastic optimizer. This paper presents a novel exploration technique for analog placement operating on a subset of tree representations of the layout—called symmetric-feasible, where the typical presence of an arbitrary number of symmetry groups of devices is directly taken into account during the search of the solution space. The computation times exhibited by this novel approach are significantly better than those of the algorithms using the traditional exploration strategy. This superior efficiency is partly due to the use of segment trees, a data structure introduced by Bentley, mainly used in computational geometry.

Automatic Synthesis of CMOS Digital/Analog Converters by Robert McKinstry Robinson Neff Doctor of Philosophy in Engineering -- Electrical Engineering and Computer Sciences University of California at Berkeley Professor Paul R. Gray, Chair Synthesis of analog functional blocks in integrated circuits offers promise for improved designer productivity. By developing module generators for commonly used analog circuit elements, a synthesis methodology may be matched to a particular application, with approaches and algorithms determined by the particular needs of target circuit type. An analog circuit designer should be able to input design specifications and underlying technology information, and a synthesis methodology should determine circuit parameter values and dimensions, creating the required mask layouts. Slow, tedious design and redesign methods should be replaced by one in which the computer finds minimum cost designs which meet performance requirements. This work implements synthesis methods for a widely used analog block, the digital/analog converter (DAC).

A flexible and efficient method for analog circuit partitioning and transistor stacking is presented. The method is based on a novel algorithm dealing with analog specific constraints and on a set of heuristics for stack generation using a pattern database. An enhanced set of stacks is obtained with respect to placement constraints. Experimental results show the effectiveness of the methods described. 1. Introduction In the last decade, some attempts have been made to develop automation for analog circuit layout design [1, 2, 3, 4]. Since the constraints for analog and digital design are different, the techniques for digital circuits cannot be easily ported to analog design. Analog physical design has to deal with special requirements for matching, symmetry, parasitics and for the variety of transistor sizes. The layout objectives in analog design target layout symmetry and device matching. Typical techniques in analog layout are large device folding, interdigitated structures for symm...

Analog design reuse is becoming more and more important in recent system-on-chip designs. In these designs electrical and physical design integration is a challenging problem specially when designing high performance analog circuits in different technologies. To solve this problem, we propose a new design methodology based on a layout-oriented synthesis approach that allows to capture design knowledge for eventual reuse with a close interaction between electrical and physical design. This methodology guarantees the fulfillment of the required performance specifications, permits to optimize various design aspects in the presence of parasitics and shortens the overall design time by avoiding laborious sizing-layout iterations. The methodology has been implemented using two knowledge-based tools dedicated to analog circuit sizing (COMDIAC) and layout generation (CAIRO). The tools allow both the design knowledge and the generated layout to be efficiently reused in similar designs. To validate the previous claims, we have chosen low-voltage low-power analog circuits as an application. Our study has led to new circuit architectures that allow very low-voltage switchedcapacitor circuit operation in standard CMOS technologies. Using the above methodology and circuit techniques, we have designed, fabricated, and tested a 1-V 14-bit Delta-Sigma A/D modulator for digital-audio applications. Two similar designs are then resynthesized in another technology demonstrating the suitability of the methodology for very high performance mixed-signal circuits. Keywords Analog Design Reuse, Analog Design Automation, Procedural Layout Generation, Delta-Sigma Modulator, Low-Voltage, Switched-Capacitor. Contents Remerciements i Resume iii Abstract v Contents vii List of Abbreviations and ...

This paper presents a performance-driven placement algorithm for automatic layout generation of analog IC's. The main innovations of our approach are essentially: (i) an integrated Place&Route optimization algorithm which is able to provide a realistic measurement of the interconnect parasitics, that is a key issue in performancedriven approaches; and (ii) the simultaneous consideration in the cost function of two levels of symmetries: global symmetry with respect to virtual axes and local symmetry affecting groups of cells. The flexibility and efficiency of the algorithm is mainly due to the use of the same slicing-tree representation for placement and global routing, and to the heuristic algorithm we propose for the global routing estimate. The feasibility of the proposed approach has been demonstrated with several practical examples. 1.-

In this paper a new topology optimization feature of a module generator environment [5-6] will be presented. The optimization is performed by removing redundant elements of objects already placed and by assessing different layout topologies of a module. This drastically reduces the length of the generator source code, because different topologies need no separate source code, but result automatically.

This paper addresses the problem of device-level placement for analog layout, focusing mainly on symmetry-related aspects. Different from most of the existent analog placement approaches, employing basically simulated annealing optimization algorithms operating on flat (absolute) spatial representations [4], our model uses a more recent topological representation called sequence-pair [14], which has the advantage of not being restricted to slicing floorplan topologies. In this paper, we are explaining how specific features essential to analog placement, as the ability to deal with complex symmetry constraints (for instance, an arbitrary number of symmetry groups of cells), can be easily handled by employing the sequence-pair representation. Several analog examples substantiate the effectiveness of our placement tool, which is already in use in an industrial environment.

In this report I formulate analog layout constraints and survey the state of the art of automatic analog layout systems, which can handle only few analog constraints, and generate less dense layout. To solve these problems I propose a new interactive analog layout methodology. It provides topological editing in the geometrical view based on Rubber-band routing. The purposes of this new methodology are i) to overcome the difficulty of control the layout parasitic elements with irregularities of analog devices and wiring effects and ii) to reduce the analog VLSI design period. After describing new concepts for that interactive methodology, I state some specific challenges.

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In this paper a new topology optimization feature of a module generator environment [5-6] will be presented. The optimization is performed by removing redundant elements of objects already placed and by assessing different layout topologies of a module. This drastically reduces the length of the generator source code, because different topologies need no separate source code, but result automatically. 1