Now that the field of automated synthesis for register transfer level integrated circuit design is beginning to mature, it is appropriate to begin developing tools for higher levels of design. At the next higher level, it is appropriate to explore behavioral and structural partitioning, answering such questions about the design as: . Should the design be implemented on a single VLSI chip, or partitioned into two or more chips, and if it is to be partitioned, where should the behavior be divided? . Should the design be implemented as a single process, with a single data path and controller, or should it be split into two or more processes, each hopefully smaller and faster than the single process design and with more potential concurrency? . Should the design be pipelined or left unpipelined, and if pipelined, how many stage divisions should there be, and where should they be placed? The goal of this research was to define the Algorithmic Level of design (also known as the Behavioral Le...

. In this article we present a structured approach to formal hardware verification by modelling circuits at the register-transfer level using a restricted form of higher-order logic. This restricted form of higher-order logic is sufficient for obtaining succinct descriptions of hierarchically designed register-transfer circuits. By exploiting the structure of the underlying hardware proofs and limiting the form of descriptions used, we have attained nearly complete automation in proving the equivalences of the specifications and implementations. A hardware-specific tool called MEPHISTO converts the original goal into a set of simpler subgoals, which are then automatically solved by a general-purpose, first-order prover called FAUST. Furthermore, the complete verification framework is being integrated within a commercial VLSI CAD framework. Keywords: hardware verification, higher-order logic 1 Introduction The past decade has witnessed the spiralling of interest within the academic com...

We illustrate the importance of a well-defined ontology for representing and integrating different types of engineering design knowledge with examples taken from bridge design. In particular, we focus on two types of knowledge: synthesis knowledge about the generation of design products, and design standards against which the generated products have to be evaluated. It is shown how both types can be represented using YMIR, an ontology for engineering design. By using the same ontological basis for the synthesis knowledge and the design standards, both types of knowledge can be used in an integrated way by the design process. in: Artificial Intelligence in Design'94, J.S. Gero and F. Sudweeks (eds.), Kluwer Academic Publishers, 1994, pp 517-534. 1.