Lava is a tool to assist circuit designers in specifying, designing, verifying and implementing hardware. It is a collection of Haskell modules. The system design exploits functional programming language features, such as monads and type classes, to provide multiple interpretations of circuit descriptions. These interpretations implement standard circuit analyses such as simulation, formal veri#cation and the generation of code for the production of real circuits.

The design and verification of a high speed sorter core is presented. We present several techniques and tools used to verify the functionality of the sorter. The sorter is a periodic sorter based on recursive butterfly networks. Having a design language that is well-suited to describing these networks has helped us to explore the design space far more effectively than is possible using conventional hardware description languages.

Dynamically re�programmable hardware �e.g. Field Programmable Gate Arrays or FPGAs � change many of our basic assumptions of what hardware is. Nor� mal hardware design focuses on the development of a static circuit of �xed size � topology and functionality. The static nature of the target design entity is re�ected in the design of CAD tools � hardware description lan� guages � net�list representations and design methodolo� gies. In this paper � the new research challenges for hard� ware description languages posed by dynamically re� programmable hardware are identi�ed. In particular� the need tospecify topological information in concert with behaviour speci�cation for e�ective realisation of limited resources is stressed. It is shown how an existing hardware description language � Ruby � can address some of these issues. Powerful parameterised recursive descriptions of but� ter�y networks are used to demonstrate how di�erent realisations can be derived from a single speci�cation. This allows di�erent con�gurations on FPGAs to be described in a systematic and high level manner.