Models of achievable routing, i.e., chip wireability, rely on estimates of available and required routing resources. Required routing resources are estimated from placement, or (a priori) using wirelength estimation models. Available routing resources are estimated by calculating a nominal "supply ", then taking into account such factors as the efficiency of the router and the impact of vias. Models of achievable routing can be used to optimize interconnect process parameters for future designs or to supply objectives that guide layout tools to promising solutions. Such models must be accurate in order to be useful, and must support empirical verification and calibration by actual routing results. In this paper, we discuss the validation of such models and we apply our validation process to three existing models. We find notable inaccuracies in the existing models when matched against real data. We then present a thorough analysis of the assumptions underlying these models; based on ...

The exciting, new field of System-Level Interconnect Prediction emerged from research of the early 1970's but it took until 1999 before a cohesive research community for interconnect prediction was established. New research results are becoming available and the last couple of years have brought both more interest and more progress in the field than in the thirty years before. This paper is an introduction to the field and provides an overview of some of the recent advances in system-level interconnect prediction. 1 Introduction As mainstream processors surpass gigahertz global clock frequencies and new design and process technologies enable even higher performance, much attention is directed toward managing the influence of interconnects in deep submicron designs. Today, interconnects are the limiting factor for both performance and density, i.e., the value and the cost of the VLSI system. Guided by better models of interconnect performance at the atomistic and grain levels of...

Performance and power of on-chip interconnects in the nanometer realm have been an increasing source of concern to designers. Network-on-Chip (NoC) structures have been proposed as a solution to achieve efficient and reliable communication. Even with the regularity of NoC structures, it is important for designers to acknowledge the physical layer interconnect issues to plan and quantify achievable performance. In this paper we present a spice-based tool: No-CIC: Network-on-Chip Interconnect Calculator, which enables NoC designers to assess the impact of interconnect circuit designs and understand the tradeoffs involved to achieve better a priori interconnect planning. NoCIC determines the interconnect performance and power based on select NoC and circuit parameters. The effects of each parameter on the interconnect performance and power are expressed through various two-dimensional and three-dimensional plots.

Models of achievable routing, i.e., chip wireability, rely on estimates of available and required routing resources. Required routing resources are estimated from placement or (a priori) using wire length estimation models. Available routing resources are estimated by calculating a nominal “supply” then take into account such factors as the efficiency of the router and the impact of vias. Models of achievable routing can be used to optimize interconnect process parameters for future designs or to supply objectives that guide layout tools to promising solutions. Such models must be accurate in order to be useful and must support empirical verification and calibration by actual routing results. In this paper, we discuss the validation of such models and we apply our validation process to three existing models. We find notable inaccuracies in the existing models when matched against real data. We then present a thorough analysis of the assumptions underlying these models. Based on this analysis, we discuss requirements for predictors of routing resources and make suggestions for a new model of achievable routing.

Conventional power estimation techniques are prone to many sources of error. With increasing dominance of coupling capacitances, capacitive coupling potentially contributes significantly to UDSM power consumption. We analyze potential sources of inaccuracy in power estimation, focusing on those due to coupling. Our results suggest that traditional power estimates can be off by as much as 50%. 1