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Rate Analysis for Embedded Systems
 ACM Trans. on Design Automation of Electronic Systems
, 1998
"... ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept, ACM Inc., 1515 Broadway, New York, N ..."
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Cited by 39 (13 self)
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ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept, ACM Inc., 1515 Broadway, New York, NY 10036 USA, fax +1 (212) 8690481, or permissions@acm.org Rate Analysis for Embedded Systems Anmol Mathur Ali Dasdan Rajesh K. Gupta y Department of Computer Science University of Illinois at UrbanaChampaign Urbana, IL 61801 September 3, 1997 Abstract. Embedded systems consist of interacting components that are required to deliver a specific functionality under constraints on execution rates and relative time separation of the components. In this paper, we model an embedded system using concurrent processes interacting through synchronization. We assume that there are rate constraints on the execution rates of processes imposed by the designer or the environment of the system, where ...
Efficient Algorithms for Optimum Cycle Mean and Optimum Cost to Time Ratio Problems
, 1999
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Symbolic Timing Verification of Timing Diagrams using Presburger Formulas
, 1997
"... We present a novel set of tools for performing symbolic timing verification of timing diagrams. The tools are multipurpose with uses in verification, derivation of synthesis constraints, and design evaluation. Our methodology is based on using techniques for manipulating Presburger formulas. We dem ..."
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Cited by 29 (4 self)
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We present a novel set of tools for performing symbolic timing verification of timing diagrams. The tools are multipurpose with uses in verification, derivation of synthesis constraints, and design evaluation. Our methodology is based on using techniques for manipulating Presburger formulas. We demonstrate using several interesting examples that the method is efficient in practice and should be considered for inclusion in commercial tools. 1 Introduction Two important areas of design automation are synthesis  the process of transforming abstract specifications into physical implementation, and verification  the process of formally ensuring designs have been properly implemented and will meet their requirements. In this paper we present novel work in the area of symbolic timing verification 1 for timing diagrams. Timing diagrams, e.g., see Figure 1, are quite popular (especially for interfaces) and are easy to understand because they correspond to execution snapshots where the ...
An event spacing experiment
 In Proceedings of the Eigth International Symposium on Advanced Research in Asynchronous Circuits and Systems
, 2002
"... timing analysis This memo is a paper submitted to Async 2002. Here’s the abstract from the next page: We describe our investigation into the spacing of events in selftimed rings. All rings that we have seen previously produce bursts of events. These bursts are caused by “drafting,” the dependence o ..."
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Cited by 22 (5 self)
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timing analysis This memo is a paper submitted to Async 2002. Here’s the abstract from the next page: We describe our investigation into the spacing of events in selftimed rings. All rings that we have seen previously produce bursts of events. These bursts are caused by “drafting,” the dependence of the delay of a gate on the time since its previous output event. We present a simple model for drafting based on the Charlie Diagrams of [5]. We use these models to identify the causes of bursts and to propose a method to control bursting behaviour. Based on this analysis, we have designed, fabricated, and tested a chip where event spacing can be switched between bursting and evenly spaced events according to an externally applied reference current. This is the first reported chip where a selftimed ring achieves evenly spaced events. x[N1] C C
Symbolic Techniques for Performance Analysis of Timed Systems based on Average Time Separation of Events
 In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems
, 1997
"... Symbolic techniques using BDDs [1] and ADDs [2] are applied to the performance analysis of (asynchronous) timed systems. We model the system as a set of probabilistic finite state machines which is analyzed as a discrete time Markov chain. The stationary probability of all reachable states is obtain ..."
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Cited by 20 (2 self)
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Symbolic techniques using BDDs [1] and ADDs [2] are applied to the performance analysis of (asynchronous) timed systems. We model the system as a set of probabilistic finite state machines which is analyzed as a discrete time Markov chain. The stationary probability of all reachable states is obtained iteratively using ADDs. Average time separation of events is symbolically calculated to determine various performance metrics. Application to a FIFO and a differential equation solver chip demonstrates the feasibility of the technique. 1. Introduction A typical objective of (asynchronous) timed systems is to achieve higher averagecase performance than the worstcase performance of any comparable synchronous system. Examples of such systems include the Intel AILD (asynchronous instruction length decoder) design, an asynchronous differential equation solver ASIC [17], and various pausible clocking interfaces [18]. To better design these systems, we need performance analysis tools that can...
Approximate Algorithms for Time Separation of Events
 In Proc. International Conf. ComputerAided Design (ICCAD
, 1997
"... We describe a polynomialtime approximate algorithm for computing minimum and maximum time separations between all pairs of events in systems specified by acyclic timing constraint graphs. Even for acyclic graphs, the problem is NPcomplete. We propose finding an approximate solution by first approx ..."
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Cited by 15 (5 self)
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We describe a polynomialtime approximate algorithm for computing minimum and maximum time separations between all pairs of events in systems specified by acyclic timing constraint graphs. Even for acyclic graphs, the problem is NPcomplete. We propose finding an approximate solution by first approximating the nonconvex feasible space with a suitable convex "envelope", and then solving the problem efficiently in the approximate convex space. Unlike previous works, our algorithm can handle both min and max type timing constraints in the same system, and has a computational complexity that is polynomial in the number of events. Although the computed separations are conservative in the worstcase, experiments indicate that our results are highly accurate in practice. 1. Introduction Finding bounds on the time separation between events has emerged as a central problem in analysis of hardware designs. The results of such an analysis can be used for interface timing verification [7]; for d...
Probabilistic Application Modeling for SystemLevel Performance Analysis
"... The objective of this paper is to introduce the Stochastic Automata Networks (SANs) as an effective formalism for application modeling in systemlevel analysis. More precisely, we present a methodology for application modeling for systemlevel power/performance analysis that can help the designer t ..."
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Cited by 13 (6 self)
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The objective of this paper is to introduce the Stochastic Automata Networks (SANs) as an effective formalism for application modeling in systemlevel analysis. More precisely, we present a methodology for application modeling for systemlevel power/performance analysis that can help the designer to select the right platform and implement a set of target multimedia applications. We also show that, under various input traces, the steadystate behavior of the application itself is characterized by very different ‘clusterings’ of the probability distributions. Having this information available, not only helps to avoid lengthy profiling simulations for predicting power and performance figures, but also enables efficient mappings of the applications onto a chosen platform. We illustrate the benefits of our methodology using the MPEG2 video decoder as the driver application.
Efficient Timing Analysis of a Class of Petri Nets
 In Proc. International Workshop on Computer Aided Verification
, 1995
"... . We describe an algebraic technique for performing timing analysis on a restricted class of Petri nets with interval time delays specified on the places of the net. The timing analysis we perform determines the extreme separation in time between specified occurrences of pairs of transitions for all ..."
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Cited by 11 (1 self)
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. We describe an algebraic technique for performing timing analysis on a restricted class of Petri nets with interval time delays specified on the places of the net. The timing analysis we perform determines the extreme separation in time between specified occurrences of pairs of transitions for all possible timed executions of the system. We present the details of the timing analysis algorithm and demonstrate polynomial running time on a nontrivial parameterized example. Petri nets with 3000 nodes and 10 16 reachable states have been analyzed using these techniques. 1 Introduction The majority of research involving the formal analysis of temporal issues in concurrent systems has focused on powerful models of concurrency and these techniques are therefore often prohibitively computationally expensive. This paper takes the approach of using a less expressive model of a concurrent system in favor of a more efficient analysis. Our model of a concurrent system is based on safe Petri ne...
Specification and Analysis of Timing Constraints for Embedded Systems
, 1997
"... Embedded systems consist of interacting hardware and software components that must deliver a specific functionality under constraints on relative timing of their actions. We describe operation delay and execution rate constraints that are useful in the context of embedded systems. A delay constraint ..."
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Cited by 9 (5 self)
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Embedded systems consist of interacting hardware and software components that must deliver a specific functionality under constraints on relative timing of their actions. We describe operation delay and execution rate constraints that are useful in the context of embedded systems. A delay constraint bounds the operation delay or specifies any of the thirteen possible constraints between the intervals of execution of a pair of operations. A rate constraint bounds the rate of execution of an operation and may be specified relative to the control flow in the system functionality. We present constraint propagation and analysis techniques to determine satisfaction of imposed constraints by a given system implementation. In contrast to previous purely analytical approaches on restricted models or statistical performance estimation based on runtime data, we present a static analysis in presence of conditionals and loops with the help of designer assists. The constraint analysis algorithms presented here have been implemented in a cosynthesis system, VULCAN, that allows the embedded system designer to interactively evaluate the effect of performance constraints on hardwaresoftware implementation tradeoffs for a given functionality. We present examples to demonstrate the application and utility of the proposed techniques.
PolynomialTime Techniques For Approximate Timing Analysis Of Asynchronous Systems
, 1998
"... As designers strive to build systems on chips with ever diminishing device sizes, and as clock speeds of gigahertz and above are being contemplated, the limitations of synchronous circuits are beginning to surface. Consequently, there has been a renewed interest in asyn chronous design techniques t ..."
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Cited by 9 (2 self)
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As designers strive to build systems on chips with ever diminishing device sizes, and as clock speeds of gigahertz and above are being contemplated, the limitations of synchronous circuits are beginning to surface. Consequently, there has been a renewed interest in asyn chronous design techniques that use judicious timing assumptions to obtain fast circuits with low hardware overhead. However, the correct operation of these circuits depend on certain timing constraints being satisfied in the actual implementation. Since statistical variations in manufacturing conditions and operating conditions result in uncertainties in component delays in a chip, it is important to analyze asynchronous systems with uncer tain component delays to check for timing constraint violations and to determine sufficient conditions for their correct operation. Unfortunately, several timing analysis problems are computationally intractable when component delays are uncertain but bounded. This the sis presents polynomialtime techniques for approximate timing analysis of asynchronous systems with bounded component delays. Although the algorithms are conservative in the worst case, experiments indicate that they are fairly accurate in practice.