We present a method for analyzing the time performance of asynchronous circuits, in particular, those derived by program transformation from concurrent programs using the synthesis approach developed by the second author. The analysis method produces a performance metric (related to the time needed to perform an operation) in terms of the primitive gate delays of the circuit. Such a metric provides a quantitative means by which to compare competing designs. Because the gate delays are functions of transistor sizes, the performance metric can be optimized with respect to these sizes. For a large class of asynchronous circuits---including those produced by using our synthesis method---these techniques produce the global optimum of the performance metric. A CAD tool has been implemented to perform this optimization. 1 Introduction Performance analysis of a synchronous computer system is simplified by an external clock that partitions the events in the system into discrete segments. In a...

Maximum and minimum mean cycle problems are important problems with many applications in performance analysis of synchronous and asynchronous digital systems including rate analysis of embedded systems, in discrete-event systems, and in graph theory. Karp's algorithm is one of the fastest and commonest algorithms for both of these problems. We present this paper mainly in the context of the maximum mean cycle problem. We show that Karp's algorithm processes more vertices and arcs than needed to find the maximum cycle mean of a digraph. This observation motivated us to propose a new graph unfolding scheme that remedies this deficiency and leads to three faster algorithms with different characteristics. Asymptotic analysis tells us that our algorithms always run faster than Karp's algorithm. Experiments on benchmark graphs confirm this fact for most of the graphs. Like Karp's algorithm, they are also applicable to both the maximum and minimum mean cycle problems. Moreover, one of them is...

ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept, ACM Inc., 1515 Broadway, New York, NY 10036 USA, fax +1 (212) 869-0481, or permissions@acm.org Rate Analysis for Embedded Systems Anmol Mathur Ali Dasdan Rajesh K. Gupta y Department of Computer Science University of Illinois at Urbana-Champaign Urbana, IL 61801 September 3, 1997 Abstract. Embedded systems consist of interacting components that are required to deliver a specific functionality under constraints on execution rates and relative time separation of the components. In this paper, we model an embedded system using concurrent processes interacting through synchronization. We assume that there are rate constraints on the execution rates of processes imposed by the designer or the environment of the system, where ...

A class of synchronized queueing networks with deterministic routing is identified to be equivalent to a subclass of timed Petri nets called marked graphs. First some structural and behavioral properties of marked graphs are recalled and used to show interesting properties of this class of performance models. In particular, ergodicity is derived from boundedness and liveness of the underlying Petri net representation, which can be efficiently computed in polynomial time on the net structure. In case of unbounded (i.e., non-strongly-connected) marked graphs, ergodicity is computed as a function of the average transition firing delays. Then the problem of computing both upper and lower bounds for the steady-state performance of timed and stochastic marked graphs is studied. In particular, linear programming problems defined on the incidence matrix of the underlying Petri nets are used to compute tight (i.e., attainable) bounds for the throughput of transitions for marked graphs with dete...

The problem of computing both upper and lower bounds for the steady-state performance of timed and stochastic Marked Graphs is studied. In particular, Linear Programming problems defined on the incidence matrix of the underlying Petri nets are used to compute tight (i.e., reachable) bounds for the throughput of transitions for live and bounded Marked Graphs with time associated with transitions. These bounds depend on the initial marking and the mean values of the delays but not on the probability distributions (thus including both the deterministic and the stochastic cases). Connections between results and techniques typical of qualitative and quantitative analysis of Petri models are stressed. 1 Introduction One of the main problems in the actual use of timed and stochastic Petri net models for the performance evaluation of large systems is the explosion of the computational complexity of the analysis algorithms. Exact performance results are usually obtained from the numerical solu...

Embedded systems consist of interacting hardware and software components that must deliver a specific functionality under constraints on relative timing of their actions. We describe operation delay and execution rate constraints that are useful in the context of embedded systems. A delay constraint bounds the operation delay or specifies any of the thirteen possible constraints between the intervals of execution of a pair of operations. A rate constraint bounds the rate of execution of an operation and may be specified relative to the control flow in the system functionality. We present constraint propagation and analysis techniques to determine satisfaction of imposed constraints by a given system implementation. In contrast to previous purely analytical approaches on restricted models or statistical performance estimation based on runtime data, we present a static analysis in presence of conditionals and loops with the help of designer assists. The constraint analysis algorithms presented here have been implemented in a cosynthesis system, VULCAN, that allows the embedded system designer to interactively evaluate the effect of performance constraints on hardwaresoftware implementation tradeoffs for a given functionality. We present examples to demonstrate the application and utility of the proposed techniques.

Back-pressure is a logical mechanism to control the flow of information on a communication channel of a latency-insensitive system (LIS) while guaranteeing that no packet is lost. Back-pressure is necessary for building open LISs and it represents an interesting design alternative also for closed LISs because it makes possible to realize highly modular implementations with more predictable features in terms of design overhead (area, power). In discussing the role of back-pressure, we revisit the logic of the necessary building blocks, and explain the impact of the system topology on the system performance.

The increasingly complex design of embedded systems creates the problems of specifying consistent and satisfiable rate constraints on process execution rates,checking them for consistency and satisfiability, computing process execution rates, and debugging rate constraint violations. The high complexity of these problems requires a complete and automated framework to help the designer in producing correct systems in shorter design time. We present such a framework and its implementation in a tool called Ratan. Experiments on large benchmarks show the suitability of the tool for an interactive debugging environment.

This paper addresses the computation of upper bounds for the throughput of transitions of live and safe deterministically or stochastically timed free choice nets. The obtained results are extensions of the marked graph case, presented by the authors in previous works. Polynomial complexity algorithms are derived using linear programming techniques. The obtained values are tight in the sense that, with the only knowledge of the net topology, the mean service times of transitions, and the routing rates at conflicts, is not possible to improve the bounds. Topics: Timed and stochastic nets. Analysis and synthesis, structure, and behaviour of nets. 1 Introduction One of the main problems in the actual use of timed and stochastic Petri net models for the performance evaluation of large systems is the explosion of the computational complexity of the analysis algorithms. In general, exact performance results are obtained from the numerical solution of a continuous time Markov chain ...

We show that Karp's algorithm processes more vertices and arcs than needed to find the maximum cycle mean of a digraph. This observation motivated us to propose a new scheme, called unfolding, that remedies this deficiency and leads to two algorithms. Both asymptotic analysis and experiments on benchmark graphs show that our algorithms run faster than Karp's algorithm. Like Karp's algorithm, they are applicable to both the maximum and minimum mean cycle problems. 1 This paper is produced using the IEEE transactions style file IEEEtran.sty with the draft option. October 6, 1996 DRAFT 2 I. Introduction The average weight of a directed cycle is the total weight of the arcs on the cycle divided by the total number of the arcs on the cycle, and is called the cycle mean. The maximum mean cycle problem for a directed graph (digraph) with cycles is to find a cycle having the maximum average weight, , called the maximum cycle mean, over all directed cycles in the graph. The minimum mean cy...