Abstract not found

Pipeline synchronization is a simple, low-cost, highbandwidth, high-reliability solution to interfaces between synchronous and asynchronous systems, or between synchronous systems operating from different clocks. The technique can sustain maximum communication bandwidth while achieving an arbitrarily low, nonzero probability of synchronization failure, P f , with the price in both latency and chip area being O(log 1 Pf ). Pipeline synchronization has been successfully applied to high-performance inter-computer communication in multicomputers [13, 15] and local-area networks [3, 7]. 1 Problem Specification Given the required rate of data transfer of E events per second between an asynchronous and a synchronous system, with each event delivering W bits of information, design an interface that will guarantee that the probability of synchronization failure be less than a given P f ? 0. The assumption is that the flow control is implemented as either a two-phase or four-phase signalin...

Min-max functions, F: Rn → Rn, arise in modelling the dynamic behaviour of discrete event systems. They form a dense subset of those functions which are homogeneous, Fi(x1 + h, · · · , xn + h) = Fi(x1, · · · , xn) + h, monotonic, ⃗x ≤ ⃗y ⇒ F (⃗x) ≤ F (⃗y), and nonexpansive in the ℓ ∞ norm—so-called topical functions—which have appeared recently in the work of several authors. Our main result characterises those min-max functions which have a (generalised) fixed point, where Fi(⃗x) = xi + h for some h ∈ R. We deduce several earlier fixed point results. The proof is inspired by Howard’s policy improvement scheme in optimal control and yields an algorithm for finding a fixed point, which appears efficient in an important special case. An extended introduction sets the context for this paper in recent work on the dynamics of topical functions.

Many advances have been made recently in the theory of circuit retiming, especially for circuits that use level-sensitive latches. In spite of this, automatic retiming tools have seen relatively little use in practice. One reason for this is the lack of good speedup results when retiming has been applied to real circuits. Another reason is that retiming has used a rather simple circuit model which reduces its utility in practice. This paper addresses both of these issues. We suggest that the reason for the poor results reported for retiming is that retiming has been applied too late in the design process when there is little flexibility for performance improvement. We give an example of using retiming early in the design process to achieve better performance while at the same time simplifying the design process itself. We then describe an extension to the retiming circuit model that includes clock skew as well as latch propagation delay, setup and hold parameters. Including these param...

Using level-sensitive latches instead of edge-triggered registers for storage elements in a synchronous system can lead to faster and less expensive circuit implementations. This advantage derives from an increased flexibility in scheduling the computations performed by the circuit. In edge-clocked circuits the amount of time available for the computation between two registers is precisely the length of the clock cycle, while in circuits using level-sensitive latches a computation can borrow time across latches thus reducing the amount of dead time in the clock cycle. In either type of circuit, achieving maximum performance requires locating the storage elements in such a way as to spread the computation uniformly across a number of clock cycles. Retiming is the process of rearranging the storage elements in a circuit to reduce the cycle time or the number of storage elements without changing the interface behavior of the circuit as viewed by an outside host. Retiming in effect resched...

Latency insensitive design has been recently proposed in literature as a way to design complex digital systems, whose functional behavior is robust with respect to arbitrary variations in interconnect latency. However, this approach does not guarantee the same robustness for the performance of the design, which indeed can experience big losses. This paper presents a simple, yet rigorous, method to (1) model the key properties of a latency insensitive system, (2) analyze the impact of interconnect latency on the overall throughput, and (3) optimize the performance of the final implementation.

This paper presents design and simulation results of two high-performance asynchronous pipeline circuits. The rst circuit is a two-phase micropipeline but uses pseudo-static Svensson-style double edge-triggered D-ip- ops (DETDFF) for data storage in place of traditional transmission gate latches or Sutherland's capture-pass latches. The second circuit is a fourphase micropipeline with burst-mode control circuits. We compare our DETDFF and four-phase implementations of a FIFO bu er with the current stateof-the-art micropipeline implementation using fourphase controllers designed by Dayand Woods for the AMULET-2 processor. We implemented Day and Woods's design and both of our designs in the MO-SIS 1:2 m CMOS process and simulated them with a 4.6V power supply and at 100 C. Our SPICE simulations show that our DETDFF and four-phase designs have 70 % and 30 % higher throughput respectively than Day and Woods's design. This higher throughput for the DETDFF design is due to latching the data on both edges of the latch control, removing the need of a reset phase and simplifying the control structures. Our four-phase design, on the other hand, has higher throughput because of the simpli ed control structures and the removal of the latch enable bu ers from the critical path. The four-phase design, though not quite as fast as the DETDFF design, requires much smaller area for data storage. 1

Symbolic techniques using BDDs [1] and ADDs [2] are applied to the performance analysis of (asynchronous) timed systems. We model the system as a set of probabilistic finite state machines which is analyzed as a discrete time Markov chain. The stationary probability of all reachable states is obtained iteratively using ADDs. Average time separation of events is symbolically calculated to determine various performance metrics. Application to a FIFO and a differential equation solver chip demonstrates the feasibility of the technique. 1. Introduction A typical objective of (asynchronous) timed systems is to achieve higher average-case performance than the worstcase performance of any comparable synchronous system. Examples of such systems include the Intel AILD (asynchronous instruction length decoder) design, an asynchronous differential equation solver ASIC [17], and various pausible clocking interfaces [18]. To better design these systems, we need performance analysis tools that can...

Approved by Dissertation Committee: This thesis is dedicated to: the gift of music pizza Beef Wellington the wines of Bordeaux mi amore

At the integration scale of System-On-Chips (SOCs), the conflicts between communication and computation will become prominent even on a chip. A big fraction of system time will shift from computation to communication. In synchronous systems, a large amount of communication time is spent on multiple-clock period wires. In this paper, we explore retiming to pipeline long interconnect wires in SOC designs. Behaviorally, it means that both computation and communication are rescheduled for parallelism. The retiming is applied to a netlist of macro-blocks, where the internal structures may not be changed and flip-flops may not be able to be inserted on some wire segments. This problem is different from that on a gate level netlist and is formulated as a wire retiming problem. Theoretical treatment and a polynomial time algorithm are presented in the paper. Experimental results showed the benefits and effectiveness of our approach.