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Efficient Verification of Parallel RealTime Systems
 In Costas Courcoubetis, editor, Computer Aided Verification
, 1997
"... This paper presents an efficient model checking algorithm for onesafe time Petri nets and a timed temporal logic. The approach is based on the idea of (1) using only differences of timing variables to be able to construct a finite representation of the set of all reachable states and (2) further r ..."
Abstract

Cited by 45 (10 self)
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This paper presents an efficient model checking algorithm for onesafe time Petri nets and a timed temporal logic. The approach is based on the idea of (1) using only differences of timing variables to be able to construct a finite representation of the set of all reachable states and (2) further reducing the size of this representation by exploiting the concurrency in the net. This reduction of the state space is possible, because the considered lineartime temporal logic is stuttering invariant. The firings of transitions are only partially ordered by causality and a given formula
Modular synthesis of timed circuits using partial order reduction
 In Electronic Notes in Theoretical Computer Science (April 2002), U. Nestmann and
, 2002
"... Abstract — This paper develops a modular synthesis algorithm for timed circuits that is dramatically accelerated by partial order reduction. This algorithm synthesizes each module in a hierarchical design individually. It utilizes partial order reduction to reduce the state space explored for the ot ..."
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Cited by 7 (6 self)
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Abstract — This paper develops a modular synthesis algorithm for timed circuits that is dramatically accelerated by partial order reduction. This algorithm synthesizes each module in a hierarchical design individually. It utilizes partial order reduction to reduce the state space explored for the other modules by considering a single interleaving of concurrently enabled transitions. This approach better manages the state explosion problem resulting in a more than 2 order of magnitude reduction in synthesis time. The improved synthesis time enables the synthesis of a larger class of timed circuits than was previously possible. I.