IONS Trent Larson Department of Computer Science Masters Degree, August 1997 ABSTRACT A simple register transfer language is good for writing hardware at multiple levels of abstraction. Such a language is a useful basis for a suite of other development tools for designing reliable hardware, such as simulators and theorem-- provers. COMMITTEE APPROVAL: Phillip Windley, Committee Chairman Kelly Flanagan, Committee Member John Higgins, Committee Member Scott Woodfield, Graduate Coordinator REGISTER TRANSFER LANGUAGES FOR HARDWARE ABSTRACTIONS A Thesis Submitted to the Department of Computer Science Brigham Young University In Partial Fulfillment of the Requirements for the Degree Master of Science c fl Trent Larson 1997 by Trent Larson August 1997 c fl Copyright 1997 by Trent Larson ii This thesis by Trent Larson is accepted in its present form by the Department of Computer Science of Brigham Young University as satisfying the thesis requirement for the degree o...

Introduction A great deal of research effort has been recently spent in the areas of formal hardware verification. Several approaches have been proposed using model checkers, induction-based approaches and higher-order logics. Three problems common to all these approches, however, include the ad hoc nature of proof organization, the lack of generalized hardware theories and the lack of support for modular verification. Ad hoc proofs require much expertise and creativity on the part of the verifier. Hardware design engineers do not want to spend large amounts of time in training on these techniques and they would rather employ their creativity in circuit design. Without generalized hardware theories, even similar hardware components must be proven from first principles. Much proof effort can be saved by creating very general theories of large classes of hardware components and specializing them for individual proofs. Like hardware development, hardware verification can be sim

A great deal of research effort has been recently spent in the areas of formal hardware verification. Several approaches have been proposed using model checkers, induction-based approaches and higher-order logics. Three problems common to all these approaches, however, include the ad hoc nature of proof organization, the lack of generalized hardware theories and the lack of support for modular verification. We address the last two problems by extending the idea of hardware combinators to structures that are tree-like in shape and develop general proof methods using these hardware combinators. The combinators provide support for modular design and verification and may be incorporated into larger verification tools while the general proof strategies reduce the verification effort required of the tool's user.