Within the context of an algebraic theory of processes, an equational specification of process cooperation is provided. Four cases are considered: free merge or interleaving, merging with communication, merging with mutual exclusion of tight regions, and synchronous process cooperation. The rewrite system behind the communication algebra is shown to be confluent and terminating (modulo its permutative reductions). Further, some relationships are shown to hold between the four concepts of merging. © 1984 Academic Press, Inc.

Abstract. This note addresses the history of process algebra as an area of research in concurrency theory, the theory of parallel and distributed systems in computer science. Origins are traced back to the early seventies of the twentieth century, and developments since that time are sketched. The author gives his personal views on these matters. He also considers the present situation, and states some challenges for the future.

A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits fulfilling the system specification will produce a particular response to a sequence of simulation commands. This style of verification has advantages over other proof methods in being readily automated and requiring less attention on the part of the user to the low-level details of the design. It has advantages over other approaches to simulation in providing more reliable results, often at a comparable cost.

In a formalism of top-down design, we consider the decomposition of behavioral specifications into interacting sequential components. The higher level of description specifies the operations to be performed in a major computation step. The goal is to incorporate a given interface specification in a lower-level specification that accounts for interactions with and among sequential components. This construction generalizes the earlier formalism of system factorization [14] to include interface protocols. It expands on the objectives of high-level synthesis by considering control-synchronization loops in scheduling. This paper presents a specification language for sequential process interaction and develops an interpretation based on finite-state-machines. Operations of minimization, composition and complementation are defined; the last of these being the key to top-down decomposition. A small example is used to illustrate the ideas. Keyword Codes: B.4.3; B.4.4; F.3.1 Keywords: Input/Outp...

In this paper we introduce a technique for modelling a subclass of CMOS circuits using the Circal process algebra. We first introduce the basic techniques for modelling hardware in an event based formalism, such as a process algebra: the level-based and the transition-based modelling techniques. Then we show how to model pMOS and nMOS transistors and how to connect them for modelling a subclass of CMOS circuits which are used in the design of asynchronous hardware.

ITL and Tempura are used for respectively the formal specification and simulation of a large scale system, namely the general purpose multi-threaded dataflow processor EP/3. This paper shows that this processor can be specified concisely within ITL and simulated with Tempura. But it also discusses some problems encountered during the specification and simulation, and indicates what should be added to solve those problems. 1 Introduction There has been a considerable debate about the use and relevance of formal methods in the development of computing systems (both software and hardware). Some claim that formal methods offer a complete solution to the problems encountered in such development. Others put the claim that formal methods are of little or no use, or that their utility is severely hindered by their cost. However, it would be over-enthusiastic to claim that a formal development technique could provide a panacea for the problem involved in developing useful computer systems. I...

Data l'importanza delle Macchine a Stati Finiti nell'hardware, sono stati sviluppati vari approcci alla loro sintesi, verifica, collaudo e diagnosi. Questo articolo presenta un approccio unificante, basato sulla rappresentazione delle funzioni booleane mediante Binary Decision Diagram (BDD) ed algoritmi di attraversamento simbolico dello spazio degli stati. I dati sperimentali sui circuiti usati in sede internazionale come casi di prova [BBKo89] ne dimostrano l'e#cacia.

This research applies formal methods in logic, verification, and synthesis to digital design engineering. The work centers on the use of applicative notation for system description and functional algebras for design development. The general goal is to develop a comprehensive methodology for constructing correct hardware

Abstract not found

Abstract not found