Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs--AlGaAs multiple-quantum-well p-i-n diodes for on-chip detection and modulation is one effective means of implementing the optoelectronic transceivers. We discuss a potential roadmap for the scaling of this hybrid optoelectronic VLSI technology as CMOS linewidths shrink and the characteristics of the hybrid optoelectronic tranceiver technology improve. An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of futur...

We present a technique for enhancing the bandwidth of gigahertz broad-band circuitry by using optimized on-chip spiral inductors as shunt-peaking elements. The series resistance of the on-chip inductor is incorporated as part of the load resistance to permit a large inductance to be realized with minimum area and capacitance. Simple, accurate inductance expressions are used in a lumped circuit inductor model to allow the passive and active components in the circuit to be simultaneously optimized. A quick and efficient global optimization method, based on geometric programming, is discussed. The bandwidth extension technique is applied in the implementation of a 2.125-Gbaud preamplifier that employs a common-gate input stage followed by a cascoded common-source stage. On-chip shunt peaking is introduced at the dominant pole to improve the overall system performance, including a 40% increase in the transimpedance. This implementation achieves a 1.6-k\Omega transimpedance and a 0.6- A i...

CONTENTS ACKNOWLEDGMENTS ..................................................................................... v LIST OF TABLES................................................................................................ vi LIST OF FIGURES ............................................................................................vii SUMMARY............................................................................................................. x Chapter I. INTRODUCTION .........................................................................1 Chapter II. BACKGROUND AND SYSTEM REQUIREMENT ................7 2.1 Background .....................................................................................7 2.2 System Requirements...................................................................24 Chapter III. A SCALEABLE CMOS CURRENT-MODE PREAMPLIFIER DESIGN AND INTEGRATION...............32 3.1 Introdu

We have designed a process-insensitive preamplifier for an optical receiver, fabricated it in several different minimum feature sizes of standard digital CMOS, and demonstrated design scaleability of this analog integrated circuit design. The same amplifier was fabricated in a 1.2 µm and two different 0.8 µm processes through the MOSIS foundry [1]. The amplifier uses a multi-stage, low-gain-per-stage approach. It has a total of 5 identical cascaded stages. Each stage is essentially a current mirror with a current gain of 3. Three of these preamplifiers have been integrated with a GaAs Metal-Semiconductor-Metal (MSM) photodetector and one with an InGaAs MSM detector by using a thin-film epilayer device separation and bonding technology [2]. This quasi-monolithic front-end of an optical receiver virtually eliminates the parasitics between the photodetector and the silicon CMOS preamplifier. We have demonstrated speed and power dissipation improvement as the minimum feature size of the transistors shrink.

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