Abstract — We consider wireless systems where the nodes operate on batteries so that energy consumption must be minimized while satisfying given throughput and delay requirements. In this context, we analyze the best modulation strategy to minimize the total energy consumption required to send a given number of bits. The total energy consumption includes both the transmission energy and the circuit energy consumption. For uncoded systems, by optimizing the transmission time and the modulation parameters we show that up to 80 % energy savings is achievable over non-optimized systems. For coded systems, we show that the benefit of coding varies with the transmission distance and the underlying modulation schemes. Index Terms — Energy efficiency, modulation optimization, MQAM, MFSK.

Abstract—A low power PSK demodulator integrated circuit (IC) has been implemented using Silicon On Insulator (SOI) CMOS technology for deep space and satellite applications. The demodulator employs double differential detection to increase its robustness to the Doppler shift caused by the movement of the space vehicle and sampling technique with 1-bit A/D converter at the front to reduce the complexity and power dissipation. In particular, digital decimation is used after sampling to achieve a low power implementation of multirate transmission. Operating at UHF frequency (435 MHz), the receiver system supports a wide range of data rates (0.1-100 Kbps). From test results, the power consumption of the demodulator circuit including the 1-bit A/D converter is below 1 mW for data rates up to 100 Kbps. Index Terms—Phase-Shift Keying (PSK), differential detection, space communications, symbol timing circuit, multirate, sampling. D I.

A 900-MHz direct-conversion receiver to detect a frequency-hopped carrier with frequency shift keying (FSK) modulation at 160 kb/s is integrated on the same chip as the transmitter. The receiver combines a low-noise amplifier with downconversion mixers and low-pass channel-select filters in quadrature channels. A digital correlating detector makes the data decisions. The received signal is dehopped when it is downconverted. The cascade noise figure is 8.6 dB, and the cascade IIP3 is 08.3 dBm. In active mode, the receiver takes 120 mA from 3 V. I.