This paper discusses design technology issues for embedded systems using processor cores, with a focus on software compilation tools. Architectural characteristics of contemporary processor cores are reviewed and tool requirements are formulated. This is followed by a comprehensive survey of both existing and new software compilation techniques that are considered important in the context of embedded processors

This work was partially supported by grants from NSF

This paper describes trends and tools for embedded systems in the areas of microcontrol and DSP. The trend analysis is from four sources: 1. A survey of over thirty DSP design groups at BNR, a telecommunication system house. 2. A second survey of over twenty BNR design groups making use of embedded processors (microcontrollers and DSP). 3. A snapshot of embedded processor use at SGS-Thomson and members of Thomson Group. 4. An overview of more general trends in embedded processor use in Europe, North America and Asia. We put particular emphasis on a relatively new category of embedded processors, application-specific instruction-set processors (ASIPs). This paper also includes an overview of FlexWare, which is currently composed of three main tools: 1. Insulin, an instruction set simulator which provides a cycle-true VHDL-based simulation environment for a user-defined instruction set. 2. CodeSyn, a retargetable compiler which takes ANSI C descriptions and maps them onto a user-defined ...

Fast processor simulators are needed for the software development ofembedded processors, for HW/SW cosimulation systems and for profiling and design of application specific processors. Such fast simulators can be generated based on the machine description language LISA. Using this language to model processor architectures enables the generation of compiled simulators on various abstraction levels, assemblers and compiler back-ends. The article discusses the requirements of software development tools on processor models and presents the approach based on the LISA language. Furthermore, the implementation of a retargetable environment consisting of compiled simulator, debugger and assembler is presented. Measurements for a verified, cycle-based LISA model of the TI TMS320C62x DSP show that this approach achieves between 37x and 170x higher simulation speed compared to a commercial simulator using a standard technique and the same accuracy level.

Efficient architecture exploration and design of application specific instruction-set processors (ASIPs) requires retargetable software development tools, in particular C compilers that can be quickly adapted to new architectures. A widespread approach is to model the target architecture in a dedicated architecture description language (ADL) and to generate the tools automatically from the ADL specification. For C compiler generation, however, most existing systems are limited either by the manual retargeting effort or by redundancies in the ADL models that lead to potential inconsistencies. We present a new approach to retargetable compilation, based on the LISA 2.0 ADL with instruction semantics, that minimizes redundancies while simultaneously achieving a high degree of automation. The key of our approach is to generate the mapping rules needed in the compiler’s code selector from the instruction semantics information. We describe the required analysis and generation techniques, and present experimental results for several embedded processors. 1.

Retargetable C compilers are key tools for efficient architecture exploration for embedded processors. In this paper we describe a novel approach to retargetable compilation based on LISA, an industrial processor modeling language for efficient ASIP design. In order to circumvent the well-known trade-off between flexibility and code quality in retargetable compilation, we propose a user-guided, semiautomatic methodology that in turn builds on a powerful existing C compiler design platform. Our approach allows to include generated C compilers into the ASIP architecture exploration loop at an early stage, thereby allowing for a more efficient design process and avoiding application /architecture mismatches. We present the corresponding methodology and tool suite and provide experimental data for two real-life embedded processors that prove the feasibility of the approach.

Programmable devices are a key technology for the design of embedded systems, such as in the consumer electronics market. Processor cores are used as building blocks for more and more embedded system designs, since they provide a unique combination of features: flexibility and reusability. Processor-based design implies that compilers capable of generating efficient machine code are necessary. However, highly efficient compilers for embedded processors are hardly available. In particular, this holds for digital signal processors (DSPs). This contribution is intended to outline different aspects of DSP compiler technology. First, we cover demands on compilers for embedded DSPs, which are partially in sharp contrast to traditional compiler construction. Secondly, we present recent advances in DSP code optimization techniques, which explore a comparatively large search space in order to achieve high code quality. Finally, we discuss the different approaches to retargetability of compilers...

This paper outlines a case study at SGS-Thomson Microelec-tronics on the development of a firmware development environment in cooperation with Thomson Consumer Electronics Components. The enviornment is for an embedded processor used for audio decompression algorithms including: MPEG2, Dolby AC-3 Surround, and Dolby Pro-logic. The enabling component of the firmware environment is a retargetable compiler which maps high-level algorithms onto the embedded processor. Although compilation is the critical technology, this experience has shown that it is insufficient and that other supporting design tools are also important. For this project, that environment includes an instruction-set simulator, a source-level debugger, a custom linker, and a compiler validation strategy. The methodologies are outlined in this paper with an emphasis on the lessons learned in this hardware-software team development. 1

this article presents contributing techniques in hardware/software co-simulation and embedded software compilation.

this article presents contributing techniques in hardware/software co-simulation and embedded software compilation