Results 1  10
of
12
Modular Verification of SRT Division
, 1996
"... . We describe a formal specification and mechanized verification in PVS of the general theory of SRT division along with a specific hardware realization of the algorithm. The specification demonstrates how attributes of the PVS language (in particular, predicate subtypes) allow the general theory to ..."
Abstract

Cited by 16 (1 self)
 Add to MetaCart
. We describe a formal specification and mechanized verification in PVS of the general theory of SRT division along with a specific hardware realization of the algorithm. The specification demonstrates how attributes of the PVS language (in particular, predicate subtypes) allow the general theory to be developed in a readable manner that is similar to textbook presentations, while the PVS table construct allows direct specification of the implementation's quotient lookup table. Verification of the derivations in the SRT theory and for the data path and lookup table of the implementation are highly automated and performed for arbitrary, but finite precision; in addition, the theory is verified for general radix, while the implementation is specialized to radix 4. The effectiveness of the automation stems from the tight integration in PVS of rewriting with decision procedures for equality, linear arithmetic over integers and rationals, and propositional logic. This example demonstrates t...
Formal Verification of the VAMP Floating Point Unit
 In CHARME 2001, volume 2144 of LNCS
, 2001
"... We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is v ..."
Abstract

Cited by 12 (6 self)
 Add to MetaCart
We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is verified on the gate level against a formal description of the IEEE standard by means of the theorem prover PVS.
STRUCTURAL EMBEDDINGS: MECHANIZATION WITH METHOD
, 1999
"... The most powerful tools for analysis of formal specifications are generalpurpose theorem provers and model checkers, but these tools provide scant methodological support. Conversely, those approaches that do provide a welldeveloped method generally have less powerful automation. It is natural, the ..."
Abstract

Cited by 5 (1 self)
 Add to MetaCart
The most powerful tools for analysis of formal specifications are generalpurpose theorem provers and model checkers, but these tools provide scant methodological support. Conversely, those approaches that do provide a welldeveloped method generally have less powerful automation. It is natural, therefore, to try to combine the betterdeveloped methods with the more powerful generalpurpose tools. An obstacle is that the methods and the tools often employ very different logics. We argue that methods are separable from their logics and are largely concerned with the structure and organization of specifications. We propose a technique called structural embedding that allows the structural elements of a method to be supported by a generalpurpose tool, while substituting the logic of the tool for that of the method. We have found this technique quite e ective and we provide some examples of its application. We also suggest how generalpurpose systems could be restructured to support this activity better.
Provably faithful evaluation of polynomials
 In Proceedings of the 21st Annual ACM Symposium on Applied Computing
, 2006
"... We provide sufficient conditions that formally guarantee that the floatingpoint computation of a polynomial evaluation is faithful. To this end, we develop a formalization of floatingpoint numbers and rounding modes in the Program Verification System (PVS). Our work is based on a wellknown formali ..."
Abstract

Cited by 3 (1 self)
 Add to MetaCart
We provide sufficient conditions that formally guarantee that the floatingpoint computation of a polynomial evaluation is faithful. To this end, we develop a formalization of floatingpoint numbers and rounding modes in the Program Verification System (PVS). Our work is based on a wellknown formalization of floatingpoint arithmetic in the proof assistant Coq, where polynomial evaluation has been already studied. However, thanks to the powerful proof automation provided by PVS, the sufficient conditions proposed in our work are more general than the original ones.
Mechanized Formal Methods: Progress and Prospects
 In Proceedings of the 16th Conference on the Foundations of Software Technology and Theoretical Computer Science, Lecture Notes in Computer Science #1180
, 1996
"... . In the decade of the 1990s, formal methods have progressed from an academic curiosity at best, and a target of ridicule at worst, to a point where the leading manufacturer of microprocessors has indicated that its next design will be formally verified. In this short paper, I sketch a plausible ..."
Abstract

Cited by 3 (0 self)
 Add to MetaCart
. In the decade of the 1990s, formal methods have progressed from an academic curiosity at best, and a target of ridicule at worst, to a point where the leading manufacturer of microprocessors has indicated that its next design will be formally verified. In this short paper, I sketch a plausible history of the developments that led to this transformation, present a snapshot of the current state of the practice, and indicate some promising directions for the future. Mindful of the title of this conference, I suggest how formal methods might have an impact on software similar to that which they have had on hardware. 1 The Past In their early days (the 1970sthough continuing to the present in some places), formal methods were associated with proofs of program correctness. This is not only a very costly and difficult exerciseit requires formalizing the semantics of real programming languages, and dealing with the scale and characteristics of real imperative programsbut i...
unknown title
"... In recent years, formal methods have emerged as an alternative approach to ensuring the quality and correctness of hardware designs, overcoming some of the limitations of traditional validation techniques such as simulation and testing. There are two main aspects to the application of formal methods ..."
Abstract
 Add to MetaCart
In recent years, formal methods have emerged as an alternative approach to ensuring the quality and correctness of hardware designs, overcoming some of the limitations of traditional validation techniques such as simulation and testing. There are two main aspects to the application of formal methods in a design process: The formal framework used to specify desired properties of a design, and the verification techniques and tools used to reason about the relationship between a specification and a corresponding implementation. We survey a variety of frameworks and techniques which have been proposed in the literature and applied to actual designs. The specification frameworks we describe include temporal logics, predicate logic, abstraction and refinement, as well as containment between!regular languages. The verification techniques presented include model checking, automatatheoretic techniques, automated theorem proving, and approaches that integrate the above methods.
Hierarchical Verification of TwoDimensional HighSpeed Multiplication in PVS: A Case Study
 FORMAL METHODS IN COMPUTERAIDED DESIGN, VOLUME 1166 OF LECTURE NOTES IN COMPUTER SCIENCE
, 1996
"... It is shown how to use the PVS specification language and proof checker to present a hierarchical formalization of a twodimensional, highspeed integer multiplier on the gate level. We first give an informal description of iterative array multiplier circuits together with a natural refinement in ..."
Abstract
 Add to MetaCart
It is shown how to use the PVS specification language and proof checker to present a hierarchical formalization of a twodimensional, highspeed integer multiplier on the gate level. We first give an informal description of iterative array multiplier circuits together with a natural refinement into vertical and horizontal stages, and then show how the various features of PVS can be used to obtain a readable, highlevel specification. The verification exploits the tight integration between rewriting, arithmetic decision procedures, and equality that is present in PVS. Altogether, this case study demonstrates that the resources of an expressive specification language and of a generalpurpose theorem prover permit highly automated verification in this domain, and can contribute to clarity, generality, and reuse.
Design Structures for Formally Verified Floating Point Units
, 1997
"... A design structure is presented to assist in the design of IEEE compliant floating point hardware. The basis of the process is an abstraction of the bitwise operations found in hardware to reals and integers. This simplifies the definition of functionality prior to going to hardware. The final desig ..."
Abstract
 Add to MetaCart
A design structure is presented to assist in the design of IEEE compliant floating point hardware. The basis of the process is an abstraction of the bitwise operations found in hardware to reals and integers. This simplifies the definition of functionality prior to going to hardware. The final design structure will include a set of general algorithms defined for floating point operations (add, sub, multiply, division, square root) which are verified with respect to the IEEE standard. The designer then instantiates the general algorithms to complete the algorithmic specification. The algorithms are then mapped to hardware, maintaining the abstraction. The result is a verified functional description of the hardware which can then be realized by conventional techniques or by refining the description to bitwise operations. This paper is a work in progress which describes the design process to get a functional description of the hardware. Current work has focused on subtractive division and...