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On the Relation Between BDDs and FDDs
 INFORMATION AND COMPUTATION
, 1995
"... Data structures for Boolean functions build an essential component of design automation tools, especially in the area of logic synthesis. The state of the art data structure is the ordered binary decision diagram (OBDD), which results from general binary decision diagrams (BDDs), also called bran ..."
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Cited by 28 (12 self)
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Data structures for Boolean functions build an essential component of design automation tools, especially in the area of logic synthesis. The state of the art data structure is the ordered binary decision diagram (OBDD), which results from general binary decision diagrams (BDDs), also called branching programs, by ordering restrictions. In the context of EXORbased logic synthesis another type of decision diagram (DD), called (ordered) functional decision diagram ((O)FDD) becomes increasingly important. We study the relation between (ordered, free) BDDs and FDDs. Both, BDDs and FDDs, result from DDs by defining the represented function in different ways. If the underlying DD is complete, the relation between both types of interpretation can be described by a Boolean transformation . This allows us to relate the FDDsize of f and the BDDsize of (f) also in the case that the corresponding DDs are free or ordered, but not (necessarily) complete. We use this property to derive...
Design of Testability Properties of AND/XOR Networks
 IFIP WG 10.5 Workshop on Applications on ReedMuller Expansion in Circuit Design
, 1993
"... ANDXOR networks include all realizations of switching functions in two and multilevel which in clude AND XOR and inverters as basic building blocks It has been shown that for many ANDXOR canonical networks and trees the test set to detect stuckatfaults and bridging faults are independent of the f ..."
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ANDXOR networks include all realizations of switching functions in two and multilevel which in clude AND XOR and inverters as basic building blocks It has been shown that for many ANDXOR canonical networks and trees the test set to detect stuckatfaults and bridging faults are independent of the function being realized This paper provides a survey of these studies and introduces certain results on some other ANDXOR Networks Here a scheme for reduction of tests on canonical mixed polarity ANDXOR networks is introduced which can be ex tended to other general mixed polarity networks In addition the independence of test sets for Consistent Generalized ReedMuller trees is presented
Testability of 2Level AND/EXOR Circuits
 in European Design & Test Conf
, 1997
"... It is often stated that AND#EXOR circuits are much easier testable than AND#OR circuits. This statement only holds for restricted classes of AND#EXOR expressions# like positive polarity Reed# Muller expressions and #xed polarity Reed#Muller ex# pressions. For these two classes of circuits good dete ..."
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Cited by 2 (0 self)
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It is often stated that AND#EXOR circuits are much easier testable than AND#OR circuits. This statement only holds for restricted classes of AND#EXOR expressions# like positive polarity Reed# Muller expressions and #xed polarity Reed#Muller ex# pressions. For these two classes of circuits good deter# ministic testability properties are known. In this paper we show that for these circuits also good random pat# tern testability can be proven. An input probability distribution is given which yields a short expected test length for biased random patterns. This is the #rst time that theoretical results on random pattern testa# bility arepresented for 2#level AND#EXOR circuit re# alizations of arbitrary Boolean functions. For more general classes of 2#level AND#EXOR circuits analogous results are not proven. We present experimental results that show that in general mini# mized 2#level AND#OR circuits are as well #or badly# testable as minimized 2#level AND#EXOR circuits. 1 Introduction M...
Testable design of GRM network with EXORtree for detecting stuckat and bridging faults,” ASPDAC 2004
"... A new testable realization of Generalized ReedMuller (GRM) expression with tree implementation of the EXORpart is presented. This solves an open problem of designing an EXORtree based GRM network that admits a universal test set. For an nvariable function, the proposed design can be tested by (2n ..."
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Cited by 2 (1 self)
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A new testable realization of Generalized ReedMuller (GRM) expression with tree implementation of the EXORpart is presented. This solves an open problem of designing an EXORtree based GRM network that admits a universal test set. For an nvariable function, the proposed design can be tested by (2n+8) test vectors, which are independent of the function and the circuitundertest (CUT). Excepting a few intergate bridging faults in the EXORtree, it detects all other single bridging (both ORand ANDtype) and all single stuckat faults. The EXORpart is designed as a tree of depth (⎡log2s ⎤ +1), where s is the number of product terms in the given GRM expression. This reduces circuit delay significantly compared to cascaded EXORpart. Further, for several benchmark circuits, the test set is found to be much smaller than those of the earlier treebased designs. 1.
Logic Synthesis Based on the ReedMuller Representation
, 1991
"... There has been recent interest in using ReedMuller equations as a way of representing and manipulating switching functions, and as a means of designing circuits based on exclusiveOR gates. Analysis of existing algorithms suggests the need for work in three areas: improving twolevel minimization al ..."
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There has been recent interest in using ReedMuller equations as a way of representing and manipulating switching functions, and as a means of designing circuits based on exclusiveOR gates. Analysis of existing algorithms suggests the need for work in three areas: improving twolevel minimization algorithms; developing algorithms for multilevel minimization; and then using the new algorithms to verify the usefulness of ReedMuller equations in practical applications. A new algorithm for the twolevel minimization of ReedMuller representations of switching functions has been developed, in which new heuristics are used to determine the best application of previously known rules for minimizing single output equations; new rules are used to link multiple output functions and to minimize incompletely specified functions. This algorithm has been implemented and benchmark comparisons with a well known minimization method shows that the new method is faster and results in smaller representat...
412
"... With the goal of making exclusiveOR formulations of switching functions more readily available to designers for implementation in LSI and VLSI technologies, we introduce the concept of an exclusiveOR space in which an exclusiveOR normal form is deJined to correspond to the conventional disjunctiv ..."
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With the goal of making exclusiveOR formulations of switching functions more readily available to designers for implementation in LSI and VLSI technologies, we introduce the concept of an exclusiveOR space in which an exclusiveOR normal form is deJined to correspond to the conventional disjunctive normal form. A geometrical representation of exclusiveOR space is described, and its various bases are listed and discussed.
On the Relation Between BDDs and FDDs (Extended Abstract)
, 1994
"... Data structures for Boolean functions build an essential component of design automation tools, especially in the area of logic synthesis. The state of the art datastructure is the ordered binary decision diagram (OBDD), which results from general binary decision diagrams (BDDs), also called branc ..."
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Data structures for Boolean functions build an essential component of design automation tools, especially in the area of logic synthesis. The state of the art datastructure is the ordered binary decision diagram (OBDD), which results from general binary decision diagrams (BDDs), also called branching programs, by ordering restrictions. In the context of EXORbased logic synthesis another type of decision diagram (DD), called (ordered) functional decision diagram ((O)FDD) becomes increasingly important. BDDs (FDDs) are directed acyclic graphs, whe...
Brief Contributions________________________________________________________________________________ Easily Testable MultipleValued Logic Circuits Derived from ReedMuller Circuits
"... AbstractÐIn 1972, Reddy showed that the binary circuits realizing ReedMuller canonical form are easily testable. In this paper, we extend Reddy's result to multiplevalued logic circuits, employing more than two discrete levels of signal. The electronic fabrication of such circuits became feas ..."
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AbstractÐIn 1972, Reddy showed that the binary circuits realizing ReedMuller canonical form are easily testable. In this paper, we extend Reddy's result to multiplevalued logic circuits, employing more than two discrete levels of signal. The electronic fabrication of such circuits became feasible due to the recent advances in integrated circuit technology. We show that, in the multiplevalued case, several new phenomena occur which allow us to asymptotically reduce the upper bound on the number of tests required for fault detection, but make the generation of tests harder. Index TermsÐMultiplevalued function, ReedMuller circuit, easily testable circuit, stuckat fault. 1
Effect of RTL Coding Style On Testability*
"... This paper illustrates the effect of functional RegisterTransfer Level (RTL) coding styles on the testability of synthesized gatelevel circuits. Thus, the advantage of having a RTL code analyzer to reduce the number of untestable faults, thereby improving the overall testability of a design is pr ..."
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This paper illustrates the effect of functional RegisterTransfer Level (RTL) coding styles on the testability of synthesized gatelevel circuits. Thus, the advantage of having a RTL code analyzer to reduce the number of untestable faults, thereby improving the overall testability of a design is presented. In addition, it has been also observed that writing efficient RTL code to improve testability reduces the total silicon area of the gatelevel circuit as well. Experimental results presented in this paper demonstrate the benefits of having a proposed RTL code analyzer. I.
Single StuckAt Fault Diagnosing Circuit of ReedMuller Canonical ExclusiveOr Sum of Product Boolean Expressions
"... Abstract: A testable design with a universal test set for single stuckat zero and stuckat one faults of ReedMuller canonical form of ExclusiveOR sum of product logic expressions is proposed. The test circuit detects almost all the single stuckat faults and needs only simple modifications for va ..."
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Abstract: A testable design with a universal test set for single stuckat zero and stuckat one faults of ReedMuller canonical form of ExclusiveOR sum of product logic expressions is proposed. The test circuit detects almost all the single stuckat faults and needs only simple modifications for variations in the circuit under test. The number of test vectors is also quite small compared with the classical method. The factor of unidentifiability is discussed and a new quantification parameter for the fault diagnosis has also been introduced. Results of Matlab simulations for a few logic functions are included. Key words: Combinational circuits, exclusiveor sum of products, ReedMuller canonical form, single stuckat faults, testability realization, universal test set