Design rules in advanced IC manufacturing processes are increasingly problematic for modern router architectures and algorithms. This paper first reviews types and causes of "difficult" design rules, as well as implications for current routing approaches. Next, some basic router components are assessed with respect to future viability. Last, the paper discusses prospects for future "coevolution" of design rules and detailed routing methods.

This paper presents a unique approach to improve yield given a routed layout. Currently after routing has been completed and compacted, it generally proceeds to verification without further modifications. However, to improve manufacturability, we introduce a concept called even wire distribution, a key element of the SURF physical design tool. To alleviate congestion, we first move vias and wires towards less dense areas in a manner which preserves the existing wiring paths. Depending on the locally available area, we then increase wire spacing to reduce defect sensitivity, without changing the area of the design. Carafe, an inductive fault analysis tool is used to evaluate the new layout. 1.0 Introduction Design for manufacturability (DFM) is becoming increasingly more important as feature sizes have shrunk to the submicron level and die sizes have increased dramatically for high performance microprocessor designs. Although progress has been made in improving manufacturing process ca...

this paper we consider the relationship of pin assignment and routing of a single-layer PGA package. This routing problem is different from general area routing in several ways:

xiv CHAPTER 1. Introduction 1 1.1 Clock Distribution : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 1 1.2 Flip Chip and Area I/O Technology : : : : : : : : : : : : : : : : : : : : : : 5 1.3 Advantages of Assigning Global Clock Tree to Package Layer : : : : : : : : 7 1.4 Dissertation Organization : : : : : : : : : : : : : : : : : : : : : : : : : : : : 10 CHAPTER 2. Clock Synthesis Scheme and Skew Constrained Net Clustering 11 2.1 Overall Scheme : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 11 2.2 Tolerable Skew Concept in Synchronous Circuits : : : : : : : : : : : : : : : 14 2.3 Intra-Cluster and Inter-Cluster Skew Constraints : : : : : : : : : : : : : : : 17 2.4 Skew Constrained Net Clustering Method : : : : : : : : : : : : : : : : : : : 19 2.5 Experimental Results : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 22 2.6 Related Work : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 25 CHAPTER 3. Planar Equal Path...

The problem of redistributing IO from bondpads on the periphery of an IC to an array of solder bumps occurs frequently in MCM layout. We show that the commonly held belief that providing enough escapes at the perimeter of the array is not sufficient to guarantee routability of the design. We analyze the Even Wiring Distribution (EWD) routing heuristic and show that it produces designs whose critical wire density is no greater that p 2 times the best possible design. Then, we employ the bound on EWD to establish a surprisingly non-monotonic relationship between bump pitch and design routability, and present our implementation of a design system that employs these principles. 1 Introduction The problem of fanning-out solder bump arrays occurs frequently in MCM layout. As array bonding for bare die becomes more prevalent, the frequency with which these fan-in/fan-out problems need to be solved will increase. At the same time, the trend of increasing IO per chip will increase the amount...

This paper presents a new performance-driven MCM r outer, namedMRC, with special consideration of crosstalk reduction. Router MRCcompletes an initial routing with an adequate performancetrade-o# including wire length, vias, number of layers, timing and crosstalk. Then a crosstalk reduction algorithm is used to make the routing solution crosstalk-free without big in#uence on other routing performances. Thus, ef- #ciently handling timing and crosstalk problems becomes the unique featureofMRC. Router MRC has been implemented and tested on MCM b enchmarks and the experimental results are very promising.

In this report I formulate analog layout constraints and survey the state of the art of automatic analog layout systems, which can handle only few analog constraints, and generate less dense layout. To solve these problems I propose a new interactive analog layout methodology. It provides topological editing in the geometrical view based on Rubber-band routing. The purposes of this new methodology are i) to overcome the difficulty of control the layout parasitic elements with irregularities of analog devices and wiring effects and ii) to reduce the analog VLSI design period. After describing new concepts for that interactive methodology, I state some specific challenges.

This paper presents a new performance-driven MCM router, named MRC, with special consideration of crosstalk reduction. Router MRC completes an initial routing with an adequate performance trade-off including wire length, vias, number of layers, timing and crosstalk. Then a crosstalk reduction algorithm is used to make the routing solution crosstalk-free without big influence on other routing performances. Thus, efficiently handling timing and crosstalk problems becomes the unique feature of MRC. Router MRC has been implemented and tested on MCM benchmarks and the experimental results are very promising.

Compared with on-chip routers, the existing commercial tools for off-chip routing have a much lower routability and often result in a large number of unrouted nets for manual routing. In this paper, we develop an effective, yet efficient, substrate routing algorithm, applying dynamic pushing to alleviate the net ordering problem and reordering and rerouting for further wire length and congestion reduction. Compared with an industrial design tool that leaves 936 nets unrouted for nine industrial designs with a total of 6100 nets, our algorithm reduces the unrouted nets to 212, a 4.5-times net number reduction and practically more design time reduction.

As IC technology advances rapidly, the dimensions of packages and PCBs are decreasing while the pin counts and routing layers keep increasing. Today, a high-performance PCB usually contains thousands of pins and more than ten signal layers. Moreover, the manufacturing constraints require all nets to be routed in the planar fashion and the designer requires nets in the same bus to be routed together without any other net. All these factors pose new challenges for the PCB routing problem, making the PCB routing so difficult that no commercial CAD software can provide an automatic solution. Today, all high-end circuit boards are routed manually, in a time-consuming manner. In this dissertation, we present new strategies for automatic PCB routing. In particular, we present novel algorithms for bus sequencing, pin assignment, bus planning, bus escape, and escape routing. ii This dissertation is dedicated to my wife, my parents and my parents-in-law and my two lovely kids, for their love and support. I definitely did not have enough time for them due to my study for the Ph.D. iii ACKNOWLEDGMENTS I am heartily thankful to my advisor, Professor Martin D.F. Wong, whose patience, encouragement, guidance and support throughout my study enabled me to complete this research work. I would also like to thank the members of my dissertation committee, Professor Sanjay Jeram Patel, Professor Deming Chen and Doctor Muhammet Mustafa Ozdal, for their constructive comments. In addition, I would like to thank all members of the VLSI CAD group at the University of Illinois at Urbana-Champaign. In particular, many thanks to Liang Deng, Lei Cheng,