Design rules in advanced IC manufacturing processes are increasingly problematic for modern router architectures and algorithms. This paper first reviews types and causes of "difficult" design rules, as well as implications for current routing approaches. Next, some basic router components are assessed with respect to future viability. Last, the paper discusses prospects for future "coevolution" of design rules and detailed routing methods.

Today’s design-manufacturing interfaces have only minimal information exchange. Lack of information on either side leads to under-performance due to too much guardbanding, and increased mask cost and increased turnaround time due to over-correction. In this work we present techniques that simultaneously utilize design and manufacturing information to improve mask quality and to reduce mask cost. 1.

Abstract. We discuss aspects of silicon quality and value left on the table by current physical implementation and manufacturing handoff flows. These aspects include the following. (1) Proper expectations with respect to guardbanding of process, statistical design, and gaps in nascent flows. (2) How manufacturing variability should be deal with by design flows, e.g., with approaches less dogmatic than traditional “correct by construction” (prevention) or “construct by correction ” (cure). (3) Opportunities to differentiate with physical implementation ‘glue ’ technologies in place-and-route. (4) New targets for 45nm and 32nm deployment such as stress/strain modeling, layout support for double-patterning lithography, and ‘design for equipment ’ synergies. 1.

Abstract — As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution enhancement techniques (RETs) are needed to correctly manufacture a chip design. The widely used RET called off-axis illumination (OAI) introduces forbidden pitches which lead to very complex design rules. It has been observed that imposing uniformity on layout designs can substantially improve printability under OAI. For metal layers, uniformity can be achieved simply by inserting dummy metal wire segments at all free spaces. Simulation results indeed show significant improvement in printability with such a dummy metal insertion approach. To minimize mask cost, it is advantageous to use dummy metal segments that are of the same size as regular metal wires due to their simple geometry. But these dummy wires are printable and hence increase coupling capacitances and potentially affect yield. The alternative